AS7C33512NTF18A
November 2004
®
3.3V 512K×18 Flowthrough Synchronous SRAM with NTDTM
Features
• Organization: 524,288 words × 18 bits
• NTD™ architecture for efficient bus operation
• Fast clock to data access: 7.5/8.5/10 ns
• Fast OE access time: 3.5/4.0 ns
• Fully synchronous operation
• Clock enable for operation hold
• Multiple chip enables for easy expansion
• 3.3 core power supply
• 2.5V or 3.3V I/O operation with separate VDDQ
• 30 mW typical standby power
• Self-timed write cycles
• Flow-through mode
• Asynchronous output enable control
• Available in 100-pin TQFP
• Interleaved or linear burst modes
• Snooze mode for standby operation
• Byte write enables
Logic Block Diagram
19
19
A[18:0]
Q
D
Address
register
burst logic
CLK
D
Q
CE0
CE1
CE2
Write delay
addr. registers
CLK
19
R/W
BWa
BWb
Control
logic
CLK
ADV / LD
FT
512K x 18
SRAM
array
LBO
ZZ
CLK
18
18
DQ [a,b]
Data
input
register
D
Q
18
18
CLK
18
CLK
CEN
Output
buffer
OE
18
OE
DQ [a,b]
Selection Guide
-75
8.5
7.5
280
120
30
-85
-10
12
Units
ns
Minimum cycle time
10
8.5
260
110
30
Maximum clock access time
Maximum operating current
Maximum standby current
10
ns
220
100
30
mA
mA
mA
Maximum CMOS standby current (DC)
11/8/04, v. 1.1
Alliance Semiconductor
P. 1 of 18
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