May 2003
AS7C33512PFS16A
AS7C33512PFS18A
®
3.3V 512K × 16/18 pipelined burst synchronous SRAM
Features
• Multiple chip enables for easy expansion
• 3.3V core power supply
• 2.5V or 3.3V I/ O operation with separate V
• Organization: 524,288 words × 16 or 18 bits
• Fast clock speeds to 166 MHz in LVTTL/ LVCMOS
• Fast clock to data access: 3.5/ 3.8/ 4.0/ 5.0 ns
• Fast OEaccess time: 3.5/ 3.8/ 4.0/ 5.0 ns
• Fully synchronous register-to-register operation
• Single register “flow-through” option
• Single-cycle deselect
DDQ
• 30 mW typical standby power in power down mode
1
• NTD™ pipeline architecture available
(AS7C33512NTD16A/ AS7C33512NTD18A)
• Asynchronous output enable control
• Available in 100-pin TQFP
• Byte write enables
1. NTD™ is a trademark of Alliance Semiconductor Corporation. All
trademarks mentioned in this document are the property of their respec-
tive owners.
Logic block diagram
Pin arrangement for TQFP
LBO
CLK
CLK
CE
CLR
ADV
ADSC
ADSP
Burst logic
512K × 16/ 18
A
NC
NC
1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
NC
VDDQ
2
Memory
array
2
2
19
NC
3
19 17
19
AddresQs
register
V
D
A[18:0]
VDDQ
4
V
5
SSQ
SSQ
CS
NC
NC
NC
6
DQpa/ NC
DQa
7
CLK
DQb
DQb
8
DQa
9
16/ 18
16/ 18
V
V
10
11
SSQ
SSQ
VDDQ
DQa
DQa
VSS
V
DDQ
GWE
BW
b
D
Q
DQb
DQb 12
DQb 13
FT 14
Byte Write
registers
TQFP 14 × 20mm
BWE
VDD
NC
VDD
ZZ
15
CLK
NC 16
17
D
Q
DQa
V
SS
2
BW
a
Byte Write
DQa
DQa
VDDQ
DQb 18
DQb 19
VDDQ 20
registers
CLK
V
V
21
SSQ
DSQSQb 22
CE0
CE1
CE2
OE
DEnableQ
register
Input
DQa
DQa
NC
Output
DQb 23
registers
registers
DQpb/ NC 24
NC 25
CE
NC
CLK
CLK
CLK
V
V
26
27
SSQ
SSQ
VDDQ
NC
V
DEnableQ
DDQ
NC 28
NC 29
NC 30
Power
down
delay
ZZ
NC
register
NC
CLK
OE
16/ 18
DQ[a,b]
Note: Pins 24 and 74 are NC for x 16.
FT
Selection guide
–166
6
–150
6.6
–133
7.5
133
4
–100
10
Units
ns
Minimum cycle time
Maximum pipelined clock frequency
Maximum pipelined clock access time
Maximum operating current
166
3.5
475
130
30
150
3.8
100
5
MHz
ns
450
110
30
425
100
30
325
90
mA
mA
mA
Maximum standby current
Maximum CMOS standby current (DC)
30
5/ 9/ 03, v.1.8.1
Alliance Semiconductor
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Copyright © Alliance Semiconductor. All rights reserved.
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