AS7C3364FT32B
AS7C3364FT36B
February 2005
®
3.3V 64K × 32/36 Flow Through Synchronous SRAM
Features
• Multiple chip enables for easy expansion
• 3.3V core power supply
• Organization: 65,536 words × 32 or 36 bits
• Fast clock to data access: 6.5/7.5/8.0/10.0 ns
• Fast OE access time: 3.5/4.0 ns
• Fully synchronous flow through operation
• Asynchronous output enable control
• Available in 100-pin TQFP package
• Individual byte write and Global write
• 2.5V or 3.3V I/O operation with separate V
• Linear or interleaved burst control
• Snooze mode for reduced power standby
• Common data inputs and data outputs
DDQ
Logic block diagram
LBO
Q0
CLK
ADV
CLK
CE
Burst logic
ADSC
ADSP
CLR
64K × 32/36
Memory
array
Q1
18
16
18
18
D
CE
CLK
Q
A
[17:0]
Address
register
36/32
36/32
GWE
BWE
BWd
D
Q
DQd
Byte write
registers
CLK
D
Q
DQc
Byte write
registers
BWc
BWb
BWa
CLK
D
Q
DQb
Byte write
registers
CLK
D
Q
DQa
Byte write
4
registers
CLK
CE0
CE1
OE
Output
buffer
D
Q
Q
CE2
Input
registers
CLK
Enable
register
CE
CLK
D
Enable
Power
down
delay
register
CLK
ZZ
36/32
OE
DQ[a:d]
Selection guide
–65
-75
8.5
7.5
250
85
-80
10
-10
12
Units
ns
Minimum cycle time
7.5
6.5
275
90
Maximum clock access time
Maximum operating current
Maximum standby current
8.0
215
75
10.0
185
75
ns
mA
mA
mA
Maximum CMOS standby current (DC)
30
30
30
30
2/8/05; v.1.2
Alliance Semiconductor
P. 1 of 19
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