February 2005
AS7C3364PFD32B
AS7C3364PFD36B
®
3.3V 64K X 32/36 pipeline burst synchronous SRAM
Features
• Linear or interleaved burst control
• Organization: 65,536 words × 32 or 36 bits
• Fast clock speeds to 200 MHz
• Fast clock to data access: 3.0/3.5/4.0 ns
• Fast OE access time: 3.0/3.5/4.0 ns
• Fully synchronous register-to-register operation
• Double-cycle deselect
• Individual byte write and global write
• Snooze mode for reduced power-standby
• Common data inputs and data outputs
• Multiple chip enables for easy expansion
• 3.3V core power supply
• 2.5V or 3.3V I/O operation with separate V
DDQ
• Asynchronous output enable control
• Available in 100-pin TQFP package
Logic block diagram
LBO
CLK
ADV
ADSC
ADSP
CLK
CE
CLR
Q0
Burst logic
64K × 32/36
Memory
array
Q1
16
14
16
16
D
CE
CLK
Q
A[15:0]
Address
register
36/32
36/32
GWE
BWE
d
D
Q
Q
Q
Q
DQ
d
Byte write
BW
registers
CLK
D
DQ
c
BW
c
Byte write
registers
CLK
D
DQ
b
BW
b
Byte write
registers
CLK
D
DQ
a
4
BW
a
Byte write
registers
CLK
D
CE0
CE1
CE2
OE
Output
registers
CLK
Q
Q
Input
registers
CLK
Enable
register
CE
CLK
D
Enable
delay
register
CLK
Power
down
ZZ
36/32
DQ [a:d]
OE
Selection guide
–200
–166
–133
7.5
133
4
Units
Minimum cycle time
5
6
ns
MHz
ns
Maximum clock frequency
Maximum clock access time
Maximum operating current
Maximum standby current
200
3.0
375
130
30
166
3.5
350
100
30
325
90
mA
mA
mA
Maximum CMOS standby current (DC)
30
1/31/05; v.1.1
Alliance Semiconductor
P. 1 of 19
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