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IC24C32A-2G 参数 Datasheet PDF下载

IC24C32A-2G图片预览
型号: IC24C32A-2G
PDF下载: 下载PDF文件 查看货源
内容描述: [EEPROM, 4KX8, Serial, CMOS, PDSO8, SOIC-8]
分类和应用: 可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟光电二极管内存集成电路
文件页数/大小: 12 页 / 54 K
品牌: ISSI [ INTEGRATED SILICON SOLUTION, INC ]
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®
IS24C32A  
IS24C64A/B  
ISSI  
65,536 bit/32,768 bit  
2-WIRE SERIAL CMOS EEPROM  
ADVANCEDINFORMATION  
JANUARY2004  
FEATURES  
DESCRIPTION  
The IS24C32A and IS24C64A/B are electrically  
• Two-Wire Serial Interface  
erasable PROM devices that use the standard 2-  
wire interface for communications. The IS24C32A  
and IS24C64A/B contain a memory array of 32K-  
bits (4K x 8) and 64K-bits (8K x 8), respectively.  
Each device is organized into 32 byte pages for  
page write mode.  
–Bi-directional data transfer protocol  
• 400 KHz (I2C Protocol) Compatibility  
• Low Power CMOS Technology  
–Standby Current less than 6 µA (5.0V)  
–Read Current less than 2 mA (5.0V)  
–Write Current less than 3 mA (5.0V)  
• Flexible Voltage Operation  
This EEPROM is offered in wide operating volt-  
ages of 1.8V to 5.5V (IS24Cxx-2) and 2.5V to 5.5V  
(IS24Cxx-3) to be compatible with most application  
voltages. ISSI designed this device family to be a  
practical, low-power 2-wire EEPROM solution.  
The devices are available in 8-pin PDIP, 8-pin  
SOIC and 8-pin TSSOP packages.  
–Vcc = 1.8V to 5.5V for –2 version  
–Vcc = 2.5V to 5.5V for –3 version  
• Hardware Data Protection  
–IS24C32A/64A: WP protects entire array  
–IS24C64B: WP protects top quarter of array  
• Sequential Read Feature  
The IS24C32A/64A/64B maintains compatibility  
with the popular 2-wire bus protocol, so it is easy  
to use in applications implementing this bus type.  
The simple bus consists of the Serial Clock wire  
(SCL) and the Serial Data wire (SDA). Using the  
bus, a Master device such as a microcontroller is  
usually connected to one or more Slave devices  
such as this device. The bit stream over the SDA  
line includes a series of bytes, which identifies a  
particular Slave device, an instruction, an address  
within that Slave device, and a series of data, if  
appropriate. The IS24C32A/64A/64B has a Write  
Protect pin (WP) to allow blocking of any write  
instruction transmitted over the bus.  
• Filtered Inputs for Noise Suppression  
• 8-pin PDIP, 8-pin SOIC and 8-pin TSSOP  
packages  
• Self time write cycle with auto clear  
5 ms @ 2.5V  
• Organization:  
–IS24C32A: 4Kx8 (128 pages of 32 bytes)  
–IS24C64A/B: 8Kx8 (256 pages of 32 bytes)  
• 32 Byte Page Write Buffer  
• High Reliability  
–Endurance: 1,000,000 Cycles  
–Data Retention: 100 Years  
• Commercial and Industrial temperature ranges  
Copyright © 2004 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time  
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to  
obtain the latest version of this device specification before relying on any published information and before placing orders for products.  
Integrated Silicon Solution, Inc. — 1-800-379-4774  
ADVANCEDINFORMATION Rev. 00A  
1
01/26/04