IS42S83200B
IS42S16160B
32Meg x 8, 16Meg x16
256-MBIT SYNCHRONOUS DRAM
SEPTEMBER 2008
OVERVIEW
FEATURES
ISSI's 256Mb Synchronous DRAM achieves high-speed
data transfer using pipeline architecture. All inputs and
outputs signals refer to the rising edge of the clock input.
The 256Mb SDRAM is organized as follows.
• Clock frequency: 166, 143, 133 MHz
• Fully synchronous; all signals referenced to a
positive clock edge
• Internal bank for hiding row access/precharge
• Power supply
VDD
3.3V 3.3V
VDDQ
IS42S83200B
IS42S16160B
IS42S83200B
IS42S16160B
8M x 8 x 4 Banks 4M x16x4 Banks
3.3V 3.3V
54-pin TSOPII
54-pin TSOPII
54-ballBGA
• LVTTL interface
• Programmable burst length
– (1, 2, 4, 8, full page)
• Programmable burst sequence:
Sequential/Interleave
• Auto Refresh (CBR)
KEY TIMING PARAMETERS
• Self Refresh
• 8K refresh cycles every 64 ms
• Random column address every clock cycle
• Programmable CAS latency (2, 3 clocks)
Parameter
-6
-7
Unit
Clk Cycle Time
CAS Latency = 3
CAS Latency = 2
6
8
7
10
ns
ns
• Burst read/write and burst read/single write
operations capability
Clk Frequency
CAS Latency = 3
CAS Latency = 2
166
125
143
100
Mhz
Mhz
• Burst termination by burst stop and precharge
command
Access Time from Clock
CAS Latency = 3
CAS Latency = 2
• Available in Industrial Temperature
5.4
6.5
5.4
6.5
ns
ns
• Available in 54-pin TSOP-II and 54-ball BGA
(x16 only)
• Available in Lead-free
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any
time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are
advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com
1
Rev. D
07/28/08
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
