IS42S81600D
IS42S16800D
16Meg x 8, 8Meg x16
128-MBIT SYNCHRONOUS DRAM
JULY 2008
OVERVIEW
FEATURES
ISSI's 128Mb Synchronous DRAM achieves high-speed
data transfer using pipeline architecture. All inputs and
outputs signals refer to the rising edge of the clock
input.The 128Mb SDRAM is organized as follows.
• Clock frequency: 166, 143, 133 MHz
• Fully synchronous; all signals referenced to a
positive clock edge
• Internal bank for hiding row access/precharge
• Power supply
VDD
3.3V 3.3V
VDDQ
IS42S81600D
4M x8x4 Banks
54-pin TSOPII
IS42S16800D
2M x16x4 Banks
54-pin TSOPII
54-ballBGA
IS42S81600D
IS42S16800D
3.3V 3.3V
• LVTTL interface
• Programmable burst length
– (1, 2, 4, 8, full page)
• Programmable burst sequence:
Sequential/Interleave
• Auto Refresh (CBR)
KEY TIMING PARAMETERS
• Self Refresh with programmable refresh periods
• 4096 refresh cycles every 64 ms
Parameter
-6
-7
-75E Unit
• Random column address every clock cycle
• Programmable CAS latency (2, 3 clocks)
Clk Cycle Time
CAS Latency = 3
CAS Latency = 2
6
8
7
10
—
7.5
ns
ns
• Burst read/write and burst read/single write
operations capability
Clk Frequency
CAS Latency = 3
CAS Latency = 2
166
125
143
100
—
133
Mhz
Mhz
• Burst termination by burst stop and precharge
command
Access Time from Clock
CAS Latency = 3
CAS Latency = 2
• Industrial Temperature Availability
• Lead-freeAvailability
5.4
6.5
5.4
6.5
—
6.5
ns
ns
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any
time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are
advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com
1
Rev. E
07/28/08
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
