IC42S81600E
IC42S16800E
16M x 8, 8M x16
128Mb SYNCHRONOUS DRAM
PRELIMINARY INFORMATION
SEPTEMBER 2008
OVERVIEW
FEATURES
ISSI'sꢀ128MbꢀSynchronousꢀDRAMꢀꢀachievesꢀhigh-speedꢀ
data transfer using pipeline architecture. All inputs and
outputs signals refer to the rising edge of the clock input.
Theꢀ128MbꢀSDRAMꢀisꢀorganizedꢀasꢀfollows.ꢀ
•ꢀ Clockꢀfrequency:ꢀ166,ꢀ143ꢀMHz
•ꢀ Fullyꢀsynchronous;ꢀallꢀsignalsꢀreferencedꢀtoꢀaꢀ
positive clock edge
•ꢀ Internalꢀbankꢀforꢀhidingꢀrowꢀaccess/precharge
•ꢀ Powerꢀsupply
Vd d
ꢀ3.3Vꢀ 3.3Vꢀꢀ
Vd d q
IC42S81600Eꢀ
4Mꢀx8ꢀx4ꢀBanksꢀ 2Mꢀx16ꢀx4ꢀBanksꢀ
54-pinꢀTSOPIIꢀ 54-pinꢀTSOPII
IC42S16800Eꢀ
IC42S81600Eꢀ
ꢀ IC42S16800Eꢀ
•ꢀ LVTTLꢀinterface
ꢀ3.3Vꢀ 3.3Vꢀꢀ
•ꢀ Programmableꢀburstꢀlengthꢀ
–ꢀ(1,ꢀ2,ꢀ4,ꢀ8,ꢀfullꢀpage)
•ꢀ Programmableꢀburstꢀsequence:ꢀ
Sequential/Interleaveꢀ
•ꢀ AutoꢀRefreshꢀ(CBR)
KEY TIMING PARAMETERS
•ꢀ SelfꢀRefresh
Parameter
-6
-7
Unit
•ꢀ 4096ꢀrefreshꢀcyclesꢀeveryꢀ64ꢀms
•ꢀ Randomꢀcolumnꢀaddressꢀeveryꢀclockꢀcycle
•ꢀ ProgrammableꢀCASꢀlatencyꢀ(2,ꢀ3ꢀclocks)
ClkꢀCycleꢀTimeꢀ
CASꢀLatencyꢀ=ꢀ3ꢀ
CASꢀLatencyꢀ=ꢀ2ꢀ
ꢀꢀ
ꢀ
ꢀ
ꢀ
6ꢀ
10ꢀ
ꢀ
7ꢀ
10ꢀ
ꢀ
ꢀ
ꢀ
nsꢀ
ns
ClkꢀFrequencyꢀ
CASꢀLatencyꢀ=ꢀ3ꢀ
CASꢀLatencyꢀ=ꢀ2ꢀ
ꢀꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
•ꢀ Burstꢀread/writeꢀandꢀburstꢀread/singleꢀwriteꢀ
166ꢀ
100ꢀ
143ꢀ
100ꢀ
Mhzꢀ
Mhz
operations capability
•ꢀ Burstꢀterminationꢀbyꢀburstꢀstopꢀandꢀprechargeꢀ
AccessꢀTimeꢀꢀfromꢀClockꢀ
CASꢀLatencyꢀ=ꢀ3ꢀ
CASꢀLatencyꢀ=ꢀ2ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
command
5.4ꢀ
6.5ꢀ
5.4ꢀ
6.5ꢀ
nsꢀ
ns
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time with-
out notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain
the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com
1
Rev. 00A
09/18/08
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
