IS24C01
IS24C02
IS24C04
IS24C08
IS24C16
ISSI
®
PAGE WRITE
The IS24CXX is capable of page-WRITE (8-byte for 24C01/
02 and 16-byte for 24C04/08/16) operation. A page-WRITE
is initiated in the same manner as a byte write, but instead
of terminating the internal write cycle after the first data word
is transferred, the master device can transmit up to N more
bytes (N=7 for 24C01/02 and N=15 for 24C04/08/16). After
the receipt of each data word, the IS24CXX responds
immediately with an ACKnowledge on SDA line, and the
three lower (24C01/24C02) or four lower (24C04/24C08/
24C16) order data word address bits are internally
incremented by one, while the higher order bits of the data
word address remain constant. If the master device should
transmit more than N+1 (N=7 for 24C01/02 and N=15 for
24C04/08/16) words, prior to issuing the STOP condition,
the address counter will “roll over,” and the previously
written data will be overwritten. Once all N+1 (N=7 for
24C01/02 and N=15 for 24C04/08/16) bytes are received
and the STOP condition has been sent by the Master, the
internal programming cycle begins. At this point, all received
data is written to the IS24CXX in a single write cycle. All
inputs are disabled until completion of the internal WRITE
cycle.
ACKNOWLEDGE POLLING
The disabling of the inputs can be used to take advantage
of the typical write cycle time. Once the stop condition is
issued to indicate the end of the host's write operation, the
IS24CXX initiates the internal write cycle. ACK polling can
be initiated immediately. This involves issuing the start
condition followed by the slave address for a write operation.
If the IS24CXX is still busy with the write operation, no ACK
will be returned. If the IS24CXX has completed the write
operation, an ACK will be returned and the host can then
proceed with the next read or write operation.
condition and the IS24CXX discontinues transmission. If
'n' is the last byte of the memory, then the data from location
'0' will be transmitted. (Refer to Current Address Read
Diagram.)
RANDOM ADDRESS READ
Selective READ operations allow the Master device to
select at random any memory location for a READ operation.
The Master device first performs a 'dummy' write operation
by sending the START condition, slave address and word
address of the location it wishes to read. After the IS24CXX
acknowledge the word address, the Master device resends
the START condition and the slave address, this time with
the R/W bit set to one. The IS24CXX then responds with its
acknowledge and sends the data requested. The master
device does not send an acknowledge but will generate a
STOP condition. (Refer to Random Address Read Diagram.)
SEQUENTIAL READ
Sequential Reads can be initiated as either a Current
Address Read or Random Address Read. After the IS24CXX
sends initial byte sequence, the master device now responds
with an ACKnowledge indicating it requires additional data
from the IS24CXX. The IS24CXX continues to output data
for each ACKnowledge received. The master device
terminates the sequential READ operation by pulling SDA
HIGH (no ACKnowledge) indicating the last data word to be
read, followed by a STOP condition.
The data output is sequential, with the data from
address n followed by the data from address n+1, ... etc.
The address counter increments by one automatically,
allowing the entire memory contents to be serially read
during sequential read operation. When the memory address
boundary (127 for IS24C01; 255 for IS24C02; 511 for
IS24C04; 1023 for IS24C08; 2047 for IS24C16) is reached,
the address counter “rolls over” to address 0, and the
IS24CXX continues to output data for each ACKnowledge
received. (Refer to Sequential Read Operation Starting with
a Random Address READ Diagram.)
READ OPERATION
READ operations are initiated in the same manner as
WRITE operations, except that the read/write bit of the
slave address is set to “1”. There are three READ operation
options: current address read, random address read and
sequential read.
CURRENT ADDRESS READ
The IS24CXX contains an internal address counter which
maintains the address of the last byte accessed, incremented
by one. For example, if the previous operation is either a
read or write operation addressed to the address location n,
the internal address counter would increment to address
location n+1. When the IS24CXX receives the Device
Addressing Byte with a READ operation (read/write bit set
to “1”), it will respond an ACKnowledge and transmit the 8-
bit data word stored at address location n+1. The master will
not acknowledge the transfer but does generate a STOP
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. D
06/25/02
5
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
