欢迎访问ic37.com |
会员登录 免费注册
发布采购

IS41LV16256-35T 参数 Datasheet PDF下载

IS41LV16256-35T图片预览
型号: IS41LV16256-35T
PDF下载: 下载PDF文件 查看货源
内容描述: 256K ×16 ( 4兆位)动态RAM与EDO页模式 [256K x 16 (4-MBIT) DYNAMIC RAM WITH EDO PAGE MODE]
分类和应用:
文件页数/大小: 19 页 / 154 K
品牌: ISSI [ INTEGRATED SILICON SOLUTION, INC ]
 浏览型号IS41LV16256-35T的Datasheet PDF文件第2页浏览型号IS41LV16256-35T的Datasheet PDF文件第3页浏览型号IS41LV16256-35T的Datasheet PDF文件第4页浏览型号IS41LV16256-35T的Datasheet PDF文件第5页浏览型号IS41LV16256-35T的Datasheet PDF文件第6页浏览型号IS41LV16256-35T的Datasheet PDF文件第7页浏览型号IS41LV16256-35T的Datasheet PDF文件第8页浏览型号IS41LV16256-35T的Datasheet PDF文件第9页  
IS41C16256
IS41LV16256
256K x 16 (4-MBIT) DYNAMIC RAM
WITH EDO PAGE MODE
FEATURES
• TTL compatible inputs and outputs
• Refresh Interval: 512 cycles/8 ms
• Refresh Mode :
RAS-Only, CAS-before-RAS
(CBR), and Hidden
• JEDEC standard pinout
• Single power supply
5V ± 10% (IS41C16256)
3.3V ± 10% (IS41LV16256)
• Byte Write and Byte Read operation via two
CAS
• Extended Temperature Range -30
o
C to 85
o
C
• Industrail Temperature Range -40
o
C to 85
o
C
ISSI
JUNE 2000
®
DESCRIPTION
The
ISSI
IS41C16256 and IS41LV16256 are 262,144 x 16-bit
high-performance CMOS Dynamic Random Access Memory. Both
products offer accelerated cycle access EDO Page Mode. EDO
Page Mode allows 512 random accesses within a single row with
access cycle time as short as 10ns per 16-bit word. The Byte Write
control, of upper and lower byte, makes the IS41C16256 and
IS41LV16256 ideal for use in 16 and 32-bit wide data bus systems.
These features make the IS41C16256 and IS41LV1626 ideally
suited for high band-width graphics, digital signal processing,
high-performance computing systems, and peripheral applications.
The IS41C16256 and
IS41LV16256
are packaged in 40-pin
400-mil SOJ and TSOP (Type II).
KEY TIMING PARAMETERS
Parameter
Max.
RAS
Access Time (t
RAC
)
Max.
CAS
Access Time (t
CAC
)
Max. Column Address Access Time (t
AA
)
Min. EDO Page Mode Cycle Time (t
PC
)
Min. Read/Write Cycle Time (t
RC
)
-35
35
10
18
12
60
-50
50
14
25
20
90
-60
60
15
30
25
110
Unit
ns
ns
ns
ns
ns
PIN CONFIGURATIONS
40-Pin TSOP (Type II)
VCC
I/O0
I/O1
I/O2
I/O3
VCC
I/O4
I/O5
I/O6
I/O7
1
2
3
4
5
6
7
8
9
10
40
39
38
37
36
35
34
33
32
31
GND
I/O15
I/O14
I/O13
I/O12
GND
I/O11
I/O10
I/O9
I/O8
40-Pin SOJ
VCC
I/O0
I/O1
I/O2
I/O3
VCC
I/O4
I/O5
I/O6
I/O7
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
GND
I/O15
I/O14
I/O13
I/O12
GND
I/O11
I/O10
I/O9
I/O8
NC
LCAS
UCAS
OE
A8
A7
A6
A5
A4
GND
PIN DESCRIPTIONS
A0-A8
I/O0-15
WE
OE
RAS
UCAS
LCAS
Vcc
GND
NC
Address Inputs
Data Inputs/Outputs
Write Enable
Output Enable
Row Address Strobe
Upper Column Address Strobe
Lower Column Address Strobe
Power
Ground
No Connection
NC
NC
WE
RAS
NC
A0
A1
A2
A3
VCC
11
12
13
14
15
16
17
18
19
20
30
29
28
27
26
25
24
23
22
21
NC
LCAS
UCAS
OE
A8
A7
A6
A5
A4
GND
NC
WE
RAS
NC
A0
A1
A2
A3
VCC
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any
errors which may appear in this publication. © Copyright 2000, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. J
06/29/00
1