IS42S83200A
(4-bank x 8,388,608 - word x 8-bit)
IS42S16160A
(4-bank x 4,194,304 - word x 16-bit)
ISSI
November 2005
®
256 Mb Synchronous DRAM
DESCRIPTION
IS42S83200A is a synchronous
256Mb
SDRAM and is
organized as 4-bank x 8,388,608-word x 8-bit; and
IS42S16160A is organized as 4-bank x 4,194,304-word x
16-bit.
All inputs and outputs are referenced to the rising
edge of CLK.
IS42S83200A
and
IS42S16160A
achieve very
high speed clock rates
up to 166MHz,
and are
suitable for main memories or
graphic
memories in computer systems.
FEATURES
ITEM
tCLK
Clock Cycle Time
(Min.)
CL=2
CL=3
IS42S83200A/16160A
-6
-
6
42
15
CL=2
CL=3
-7
-
7
45
20
-
5.4
63
-75
10
7.5
45
20
6
5.4
67.5
110
Unit
ns
ns
ns
ns
ns
ns
ns
mA
mA
mA
tRAS Active to Precharge Command Period (Min.)
(Min.)
tRCD Row to Column Delay
tAC
tRC
Icc1
Icc6
Access Time from CLK
Ref /Active Command Period
Operation Current (Single Bank)
Self Refresh Current
(Max.)
(Min.)
(Max.)
IS42S83200A
IS42S16160A
-
5
60
-
130
3
-
130
3
-
3
(Max.) -6,-7,-75
- Single 3.3V ±0.3V power supply
- Max. Clock frequency:
-6:166MHz<3-3-3>
-7:143MHz<3-3-3>
-75:133MHz<3-3-3>
- Fully synchronous operation referenced to clock rising edge
- 4-bank operation controlled by BA0,BA1(Bank Address)
- /CAS latency- 2/3 (programmable)
- Burst length- 1/2/4/8/FP (programmable)
- Burst type- Sequential and interleave burst (programmable)
- Byte Control- DQML and DQMU (IS42S16160A)
- Random column access
- Auto precharge / All bank precharge controlled by A10
- Auto and self refresh
- 8192 refresh cycles /64ms(4 banks concurrent refresh)
- LVTTL Interface
- Row address A0-12 /Column address A0-9(x8) / A0-8(x16)
- Package:
400-mil, 54-pin Thin Small Outline (TSOP II) with 0.8mm lead pitch
-
Lead-free available
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
11/01/05
1
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
