IS42S16400D-7TLI 参数 Datasheet PDF下载

IS42S16400D

ISSI

®

7. READs or WRITEs to bank m listed in the Command (Action) column include READs or WRITEs with auto precharge enabled

and READs or WRITEs with auto precharge disabled.

8. CONCURRENT AUTO PRECHARGE: Bank n will initiate the AUTO PRECHARGE command when its burst has been inter-

rupted by bank m’s burst.

9. Burst in bank n continues as initiated.

10. For a READ without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the

READ on bank n, CAS latency later (Consecutive READ Bursts).

11. For a READ without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt

the READ on bank n when registered (READ to WRITE). DQM should be used one clock prior to the WRITE command to prevent

bus contention.

12. For a WRITE without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt

the WRITE on bank n when registered (WRITE to READ), with the data-out appearing CAS latency later. The last valid WRITE to

bank n will be data-in registered one clock prior to the READ to bank m.

13. For a WRITE without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt

the WRITE on bank n when registered (WRITE to WRITE). The last valid WRITE to bank n will be data-in registered one clock

prior to the READ to bank m.

14. For a READ with auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the

READ on bank n, CAS latency later. The PRECHARGE to bank n will begin when the READ to bank m is registered (Fig CAP 1).

15. For a READ with auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt the

READ on bank n when registered. DQM should be used two clocks prior to the WRITE command to prevent bus contention. The

PRECHARGE to bank n will begin when the WRITE to bank m is registered (Fig CAP 2).

16. For a WRITE with auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the

WRITE on bank n when registered, with the data-out appearing CAS latency later. The PRECHARGE to bank n will begin after

t

WR

is met, where t

WR

begins when the READ to bank m is registered. The last valid WRITE to bank n will be data-in registered

one clock prior to the READ to bank m (Fig CAP 3).

17. For a WRITE with auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt the

WRITE on bank n when registered. The PRECHARGE to bank n will begin after t

WR

is met, where t WR begins when the WRITE

to bank m is registered. The last valid WRITE to bank n will be data registered one clock prior to the WRITE to bank m (Fig CAP 4).

Integrated Silicon Solution, Inc. — www.issi.com —

1-800-379-4774

Rev. C

07/05/06

11