®
IS42S32200B
ISSI
REGISTER DEFINITION
Mode Register
until it is programmed again or the device loses power.
The mode register is used to define the specific mode of
operation of the SDRAM. This definition includes the
selection of a burst length, a burst type, a CAS\ latency,
an operating mode and a write burst mode, as shown in
MODE REGISTER DEFINITION.
Mode register bits M0-M2 specify the burst length, M3
specifiesthetypeofburst (sequentialorinterleaved), M4-M6
specify the CAS latency, M7 and M8 specify the operating
mode, M9 specifies the WRITE burst mode, and M10 and
M11 and M12 are reserved for future use.
The mode register is programmed via the LOAD MODE
REGISTER command and will retain the stored information
The mode register must be loaded when all banks are idle,
and the controller must wait the specified time before
initiating the subsequent operation. Violating either of
these requirements will result in unspecified operation.
MODE REGISTER DEFINITION
Address Bus
BA0,1
A10/AP A9
A8 A7
A6
A5 A4
A3 A2
A1
A0
0(1)
0(1)
Burst Type
M3Type
0
1
Sequential
Interleaved
Burst Length
M2 M1 M0 Sequential Interleave
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
2
4
1
2
4
8
8
Reserved
Reserved
Reserved
Full Page
Reserved
Reserved
Reserved
Reserved
Latency Mode
M6 M5 M4 CAS Latency
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved
Reserved
2
3
Reserved
Reserved
Reserved
Reserved
MRS
M8 M7 MRS
0
—
0
—
Mode Register Set
All Other States Reserved
Write Burst Mode
M9
0
Mode
Burst Write
Single-Bit Write
Note:
1. Maintain low during Mode Register Set.
1
12
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. 00C
09/29/03
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
