IS42S32400B
PIN FUNCTIONS
Symbol
A0-A11
Type
Input Pin
Function (In Detail)
ISSI
®
Address Inputs: A0-A11 are sampled during the ACTIVE
command (row-address A0-A11) and READ/WRITE command (column address A0-
A7), with A10 defining auto precharge) to select one location out of the memory array in
the respective bank. A10 is sampled during a PRECHARGE command to determine if
all banks are to be precharged (A10 HIGH) or bank selected by
BA0, BA1 (LOW). The address inputs also provide the op-code during a LOAD MODE
REGISTER command.
Bank Select Address: BA0 and BA1 defines which bank the ACTIVE, READ, WRITE or
PRECHARGE command is being applied.
CAS,
in conjunction with the
RAS
and
WE,
forms the device command. See the
"Command Truth Table" for details on device commands.
The CKE input determines whether the CLK input is enabled. The next rising edge of the
CLK signal will be valid when is CKE HIGH and invalid when LOW. When CKE is LOW,
the device will be in either power-down mode, clock suspend mode, or self refresh
mode. CKE is an asynchronous input.
CLK is the master clock input for this device. Except for CKE, all inputs to this device
are acquired in synchronization with the rising edge of this pin.
The
CS
input determines whether command input is enabled within the device.
Command input is enabled when
CS
is LOW, and disabled with
CS
is HIGH. The device
remains in the previous state when
CS
is HIGH.
DQM0 - DQM3 control the four bytes of the I/O buffers (DQ0-DQ31). In read
mode, DQMn control the output buffer. When DQMn is LOW, the corresponding buffer
byte is enabled, and when HIGH, disabled. The outputs go to the HIGH impedance
state whenDQMn is HIGH. This function corresponds to
OE
in conventional DRAMs. In
write mode, DQMn control the input buffer. When DQMn is LOW, the corresponding
buffer byte is enabled, and data can be written to the device. When DQMn is HIGH,
input data is masked and cannot be written to the device.
Data on the Data Bus is latched on these pins during Write commands, and buffered
after Read commands.
RAS,
in conjunction with
CAS
and
WE,
forms the device command. See the "Command
Truth Table" item for details on device commands.
WE,
in conjunction with
RAS
and
CAS,
forms the device command. See the "Command
Truth Table" item for details on device commands.
V
DDQ
is the output buffer power supply.
V
DD
is the device internal power supply.
V
SSQ
is the output buffer ground.
V
SS
is the device internal ground.
BA0, BA1
CAS
CKE
Input Pin
Input Pin
Input Pin
CLK
CS
Input Pin
Input Pin
DQM0-DQM3
Input Pin
DQ0-DQ31
RAS
WE
V
DDQ
V
DD
V
SSQ
V
SS
Input/Output Pin
Input Pin
Input Pin
Power Supply Pin
Power Supply Pin
Power Supply Pin
Power Supply Pin
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
PRELIMINARY INFORMATION Rev. 00G
06/15/06
5
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
