欢迎访问ic37.com |
会员登录 免费注册
发布采购

IS42S32400B-7T 参数 Datasheet PDF下载

IS42S32400B-7T图片预览
型号: IS42S32400B-7T
PDF下载: 下载PDF文件 查看货源
内容描述: 4Meg ×32 128兆位同步DRAM [4Meg x 32 128-MBIT SYNCHRONOUS DRAM]
分类和应用: 存储内存集成电路光电二极管动态存储器时钟
文件页数/大小: 60 页 / 625 K
品牌: ISSI [ INTEGRATED SILICON SOLUTION, INC ]
 浏览型号IS42S32400B-7T的Datasheet PDF文件第8页浏览型号IS42S32400B-7T的Datasheet PDF文件第9页浏览型号IS42S32400B-7T的Datasheet PDF文件第10页浏览型号IS42S32400B-7T的Datasheet PDF文件第11页浏览型号IS42S32400B-7T的Datasheet PDF文件第13页浏览型号IS42S32400B-7T的Datasheet PDF文件第14页浏览型号IS42S32400B-7T的Datasheet PDF文件第15页浏览型号IS42S32400B-7T的Datasheet PDF文件第16页  
®
IS42S32400B  
ISSI  
CKE RELATED COMMAND TRUTH TABLE(1)  
CKE  
Current State  
Self-Refresh(S.R.)  
Operation  
n-1  
H
L
n
X
H
H
H
H
L
CS  
X
H
L
RAS  
X
X
H
H
L
CAS  
X
X
H
L
WE Address  
INVALID,CLK(n-1)wouldexitS.R.  
Self-RefreshRecovery(2)  
Self-RefreshRecovery(2)  
Illegal  
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
L
X
X
L
X
L
L
X
Illegal  
L
L
X
X
X
H
L
X
MaintainS.R.  
L
X
H
L
X
X
H
H
L
X
Self-RefreshRecovery Idle After tRC  
H
H
H
H
H
H
H
H
L
H
H
H
H
L
X
Idle After tRC  
Illegal  
X
L
X
Illegal  
L
X
X
H
L
X
Beginclocksuspendnextcycle(5)  
H
L
X
H
H
L
X
Beginclocksuspendnextcycle(5)  
L
X
Illegal  
L
L
X
Illegal  
L
L
X
X
X
X
X
X
X
X
H
L
X
Exitclocksuspendnextcycle(2)  
H
L
X
X
X
X
X
H
L
X
X
X
X
X
X
H
L
X
Maintainclocksuspend  
L
X
Power-Down(P.D.)  
BothBanksIdle  
INVALID,CLK(n-1)wouldexitP.D.  
EXITP.D.-->Idle(2)  
H
L
X
H
L
X
Maintainpowerdownmode  
L
X
RefertooperationsinOperativeCommandTable  
RefertooperationsinOperativeCommandTable  
RefertooperationsinOperativeCommandTable  
Auto-Refresh  
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
L
L
L
L
X
RefertooperationsinOperativeCommandTable  
RefertooperationsinOperativeCommandTable  
RefertooperationsinOperativeCommandTable  
RefertooperationsinOperativeCommandTable  
Self-Refresh(3)  
L
L
L
Op-Code  
H
L
X
H
L
X
X
H
L
X
X
X
H
L
L
L
L
L
L
L
X
RefertooperationsinOperativeCommandTable  
L
L
L
L
Op-Code  
(3)  
Power-Down  
X
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Anystate  
RefertooperationsinOperativeCommandTable  
Beginclocksuspendnextcycle(4)  
Exitclocksuspendnextcycle  
H
H
L
otherthan  
listedabove  
H
L
Maintainclocksuspend  
L
Notes:  
1. H : High level, L : low level, X : High or low level (Don’t care).  
2. CKE Low to High transition will re-enable CLK and other inputs asynchronously. A minimum  
setup time must be satisfied  
before any command other than EXIT.  
3. Power down and Self refresh can be entered only from the both banks idle state.  
4. Must be legal command as defined in Operative Command Table.  
5. Illegal if tXSR is not satisfied.  
12  
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774  
PRELIMINARY INFORMATION Rev. 00G  
06/15/06