IS42S16100E
IS45S16100E
512K Words x 16 Bits x 2 Banks
16Mb SYNCHRONOUS DYNAMIC RAM
FEATURES
• Clock
frequency: 200, 166, 143 MHz
• Fully synchronous; all signals referenced to a
positive clock edge
• Two banks can be operated simultaneously and
independently
• Dual internal bank controlled by A11 (bank select)
• Single 3.3V power supply
• LVTTL interface
• Programmable burst length
– (1, 2, 4, 8, full page)
• Programmable burst sequence:
Sequential/Interleave
• 2048 refresh cycles every 32ms (Com, Ind, A1
grade) or 16ms (A2 grade)
• Random column address every clock cycle
• Programmable CAS latency (2, 3 clocks)
• Burst read/write and burst read/single write
operations capability
• Burst termination by burst stop and
precharge command
• Byte controlled by LDQM and UDQM
• Packages: 400-mil 50-pin TSOP-II and 60-ball
TF-BGA
• Temperature Grades:
Commercial (0
o
C to +70
o
C)
Industrial (-40
o
C to +85
o
C)
Automotive A1 (-40
o
C to +85
o
C)
Automotive A2 (-40
o
C to +105
o
C)
SEPTEMBER 2009
DESCRIPTION
ISSI
’s 16Mb Synchronous DRAM IS42/4516100E is
organized as a 524,288-word x 16-bit x 2-bank for
improved performance. The synchronous DRAMs
achieve high-speed data transfer using pipeline
architecture. All inputs and outputs signals refer to the
rising edge of the clock input.
PIN CONFIGURATIONS
50-Pin TSOP (Type II)
VDD
DQ0
DQ1
GNDQ
DQ2
DQ3
VDDQ
DQ4
DQ5
GNDQ
DQ6
DQ7
VDDQ
LDQM
WE
CAS
RAS
CS
A11
A10
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
GND
DQ15
DQ14
GNDQ
DQ13
DQ12
VDDQ
DQ11
DQ10
GNDQ
DQ9
DQ8
VDDQ
NC
UDQM
CLK
CKE
NC
A9
A8
A7
A6
A5
A4
GND
PIN DESCRIPTIONS
A0-A10
A11
A0-A7
DQ0 to DQ15
CLK
CKE
CS
RAS
Row Address Input
Bank Select Address
Column Address Input
Data DQ
System Clock Input
Clock Enable
Chip Select
Row Address
Strobe Command
CAS
WE
LDQM
VDD
GND
VDDQ
NC
Column Address Strobe Command
Write Enable
Lower Bye, Input/Output Mask
Power
Ground
Power Supply for DQ Pin
No Connection
UDQM Upper Bye, Input/Output Mask
GNDQ Ground for DQ Pin
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat-
est version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com
Rev. D
08/24/09
1
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
