IS42S83200C
IS42S16160C
A. MODE REGISTER FIELD TABLE TO PROGRAM MODES
Register Programmed with Normal MRS
Address
BA0
BA1
A12
A11
A10/AP
A9*2
A8
A7
A6
A5
A4
A3
A2
A1
A0
Function
CAS Latency
BT
Burst Length
0
0
0
0
0
0
0
0
Normal MRS Mode
CAS Latency
Burst Type
Burst Length
A6
0
0
0
0
1
1
1
1
A5
0
0
1
1
0
0
1
1
A4
0
1
0
1
0
1
0
1
Latency
Reserved
1
A3
0
1
Type
Sequential
Interleave
A2 A1 A0
BT=0
1
2
4
BT=1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
2
4
8
2
3
8
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Full Page
Reserved
Reserved
Reserved
Reserved
B. POWER UP SEQUENCE
1. Apply power and attempt to maintain CKE at a high state and all other inputs may be undefined.
- Apply VDD before or at the same time as VDDQ.
2. Maintain stable power, stable clock and NOP input condition for a minimum of 200us.
3. Issue precharge commands for all banks of the devices.
4. Issue 2 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode register.
C. BURST SEQUENCE
STARTING COLUMN
ADDRESS
ORDER OF ACCESSES WITHIN A BURST
TYPE=SEQUENTIAL TYPE=INTERLEAVED
BURST LENGTH
A0
0
2
0-1
0-1
1
1-0
1-0
A1 A0
0
0
1
1
0
1
0
1
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
4
A2 A1 A0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
8
Cn, Cn+1, Cn+2, Cn+3,
Cn+4..., …Cn-1, Cn…
Full Page (y)
N=A0 – A8 (location 0 – y)
Not Supported
NOTE:
1. For full-page accesses: y = 512.
2. For a burst length of two, A1–A8 select the block-of-two burst; A0 selects the starting column within the block.
3. For a burst length of four, A2–A8 select the block-of-four burst; A0–A1 select the starting column within the block.
4. For a burst length of eight, A3–A8 select the block-of-eight burst; A0–A2 select the starting column within the block.
5. For a full-page burst, the full row is selected and A0–A8 select the starting column.
6. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block.
7. For a burst length of one, A0–A8 select the unique column to be accessed, and mode register bit M3 is ignored.
14
Integrated Silicon Solution, Inc. — www.issi.com
Rev. C
04/02/09
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
