IS42S83200D, IS42S16160D
IS45S83200D, IS45S16160D
PIN CONFIGURATION
54-ball fBGA for x16
(Top View) (8.00 mm x 13.00 mm Body, 0.8 mm Ball Pitch)
package code: B
1
2 3 4 5 6 7 8 9
A
B
C
D
E
F
G
H
J
VSS DQ15 VSSQ
DQ14 DQ13 VDDQ
DQ12 DQ11 VSSQ
DQ10 DQ9 VDDQ
DQ8
NC
VSS
CKE
A9
A6
A4
VDDQ DQ0 VDD
VSSQ DQ2 DQ1
VDDQ DQ4 DQ3
VSSQ DQ6 DQ5
VDD DQML DQ7
CAS
BA0
A0
A3
RAS
BA1
A1
A2
WE
CS
A10
VDD
DQMH CLK
A12
A8
VSS
A11
A7
A5
PIN DESCRIPTIONS
A0-A12
A0-A8
BA0, BA1
DQ0 to DQ15
CLK
CKE
CS
RAS
CAS
Row Address Input
Column Address Input
Bank Select Address
Data I/O
System Clock Input
Clock Enable
Chip Select
Row Address Strobe Command
Column Address Strobe Command
WE
DQML
DQMH
V
dd
Vss
V
ddq
V
ssq
NC
Write Enable
x16 Lower Byte Input/Output Mask
x16 Upper Byte Input/Output Mask
Power
Ground
Power Supply for I/O Pin
Ground for I/O Pin
No Connection
Integrated Silicon Solution, Inc. — www.issi.com
Rev. B
06/11/09
5
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
