®
IS61C1024AL, IS64C1024AL
ISSI
AC WAVEFORMS
WRITE CYCLE NO. 1(CE1 Controlled, OE is HIGH or LOW) (1 )
t
WC
VALID ADDRESS
ADDRESS
CE1
t
t
SCE1
SCE2
t
SA
t
HA
CE2
t
AW
t
t
PWE1
PWE2
WE
t
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
DOUT
t
SD
t
HD
DATAIN VALID
DIN
CE2_WR1.eps
WRITE CYCLE NO. 2(OE is HIGH During Write Cycle) (1,2)
t
WC
ADDRESS
VALID ADDRESS
t
HA
OE
LOW
HIGH
CE1
CE2
t
AW
t
PWE1
WE
t
HZWE
t
LZWE
t
SA
HIGH-Z
DATA UNDEFINED
DOUT
t
SD
t
HD
DATAIN VALID
DIN
CE2_WR2.eps
Notes:
1. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states
to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced
to the rising or falling edge of the signal that terminates the Write.
2. I/O will assume the High-Z state if OE = VIH.
8
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
01/24/05
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
