IS61LF25672A IS61LF51236A IS61LF102418A
IS61VF25672A IS61VF51236A IS61VF102418A
ISSI
7
V
DDQ
NC
NC
NC
DQa
V
DDQ
DQa
NC
V
DDQ
DQa
NC
V
DDQ
NC
DQa
NC
ZZ
V
DDQ
®
119 BGA PACKAGE PIN CONFIGURATION
1M
X
18 (TOP VIEW)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DDQ
NC
NC
DQb
NC
V
DDQ
NC
DQb
V
DDQ
NC
DQb
V
DDQ
DQb
NC
NC
NC
V
DDQ
2
A
A
A
NC
DQb
NC
DQb
NC
V
DD
DQb
NC
DQb
NC
DQPb
A
A
TMS
3
A
A
A
Vss
Vss
Vss
BWb
Vss
NC
Vss
Vss
Vss
Vss
Vss
MODE
A
TDI
4
ADSP
ADSC
V
DD
NC
CE
OE
ADV
GW
V
DD
CLK
NC
BWE
A
1
*
A
0
*
V
DD
NC
TCK
5
A
A
A
Vss
Vss
Vss
Vss
Vss
NC
Vss
BWa
Vss
Vss
Vss
NC
A
TDO
6
A
A
A
DQPa
NC
DQa
NC
DQa
V
DD
NC
DQa
NC
DQa
NC
A
A
NC
Note:
* A
0
and A
1
are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol
A
A0, A1
ADV
ADSP
ADSC
GW
CLK
CE
BWE
Pin Name
Address Inputs
Synchronous Burst Address Inputs
Synchronous Burst Address
Advance.
Address Status Processor
Address Status Controller
Global Write Enable
Synchronous Clock
Synchronous Chip Select
Byte Write Enable
Symbol
OE
ZZ
MODE
TCK, TDO
TMS, TDI
NC
DQa-DQb
DQPa-Pb
V
DD
V
DDQ
Vss
Pin Name
Output Enable
Power Sleep Mode
Burst Sequence Selection
JTAG Pins
No Connect
Data Inputs/Outputs
Data Inputs/Outputs
Power Supply
Output Power Supply
Ground
BWx
(x=a,b) Synchronous Byte Write Controls
6
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. E
04/21/06
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
