IS61LV12816
WRITE CYCLE NO. 4
(LB,
UB
Controlled, Back-to-Back Write)
(1,3)
t
WC
ADDRESS
ADDRESS 1
ISSI
t
WC
ADDRESS 2
®
OE
t
SA
CE
LOW
WE
t
HA
t
SA
t
PBW
t
PBW
WORD 2
t
HA
UB, LB
WORD 1
t
HZWE
D
OUT
HIGH-Z
t
LZWE
t
HD
DATA
IN
VALID
DATA UNDEFINED
t
SD
D
IN
t
SD
DATA
IN
VALID
t
HD
UB_CEWR4.eps
Notes:
1. The internal Write time is defined by the overlap of
CE
= LOW,
UB
and/or
LB
= LOW, and
WE
= LOW. All signals must be
in valid states to initiate a Write, but any can be deasserted to terminate the Write. The
t
SA
,
t
HA
,
t
SD
, and
t
HD
timing is
referenced to the rising or falling edge of the signal that terminates the Write.
2. Tested with
OE
HIGH for a minimum of 4 ns before
WE
= LOW to place the I/O in a HIGH-Z state.
3.
WE
may be held LOW across many address cycles and the
LB, UB
pins can be used to control the Write function.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. C
02/05/2003
11
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
