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IS61SF12832-10TQ 参数 Datasheet PDF下载

IS61SF12832-10TQ图片预览
型号: IS61SF12832-10TQ
PDF下载: 下载PDF文件 查看货源
内容描述: 128K ×32 , 128K ×36流同步,通过静态RAM [128K x 32, 128K x 36 SYNCHRONOUS FLOW-THROUGH STATIC RAM]
分类和应用:
文件页数/大小: 16 页 / 114 K
品牌: ISSI [ INTEGRATED SILICON SOLUTION, INC ]
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IS61SF12832
IS61SF12836
128K x 32, 128K x 36 SYNCHRONOUS
FLOW-THROUGH STATIC RAM
FEATURES
• Fast access times: 7.5 ns, 8 ns, 8.5 ns, 10 ns,
and 12 ns
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data
inputs and control signals
• Pentium™ or linear burst sequence control
using MODE input
• Three chip enables for simple depth expansion
and address pipelining
• Common data inputs and data outputs
• JEDEC 100-Pin TQFP and
119-pin PBGA package
• Single +3.3V +10%, –5% power supply
• Power-down snooze mode
ISSI
®
APRIL 2001
DESCRIPTION
The
ISSI
IS61SF12832 and IS61SF12836 are high-speed
synchronous static RAM designed to provide a burstable,
high-performance memory for high speed networking and
communication applications. It is organized as 131,072
words by 32 bits or 36 bits, fabricated with
ISSI
's advanced
CMOS technology. The device integrates a 2-bit burst counter,
high-speed SRAM core, and high-drive capability outputs into
a single monolithic circuit. All synchronous inputs pass
through registers controlled by a positive-edge-triggered
single clock input.
Write cycles are internally self-timed and are initiated by the
rising edge of the clock input. Write cycles can be from one to
four bytes wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be written.
BW1
controls DQa,
BW2
controls DQb,
BW3
controls DQc,
BW4
controls DQd, conditioned by
BWE
being LOW. A LOW
on
GW
input would cause all bytes to be written.
Bursts can be initiated with either
ADSP
(Address Status
Processor) or
ADSC
(Address Status Cache Controller) input
pins. Subsequent burst addresses can be generated internally
and controlled by the
ADV
(burst address advance) input pin.
The mode pin is used to select the burst sequence order,
Linear burst is achieved when this pin is tied LOW. Interleave
burst is achieved when this pin is tied HIGH or left floating.
FAST ACCESS TIME
Symbol
t
KQ
t
KC
Parameter
Clock Access Time
Cycle Time
Frequency
7.5
7.5
8.5
117
8
8
10
100
8.5
8.5
11
90
10
10
15
66
12
12
15
66
Units
ns
ns
MHz
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any
errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01
1