IS62WV12816ALL,
IS62WV12816BLL
ISSI
55 ns
Min. Max.
55
45
45
0
0
45
40
25
0
—
5
—
—
—
—
—
—
—
—
—
20
—
70 ns
Min. Max.
70
60
60
0
0
60
50
30
0
—
5
—
—
—
—
—
—
—
—
—
20
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
—
—
—
—
—
—
—
—
—
20
—
®
WRITE CYCLE SWITCHING CHARACTERISTICS
(1,2)
(Over Operating Range)
Symbol
Parameter
Write Cycle Time
45ns
Min. Max.
45
35
35
0
0
35
35
20
0
—
5
t
WC
t
SCS1/
t
SCS2
CS1/CS2
to Write End
t
AW
Address Setup Time to Write End
t
HA
t
SA
t
PWB
t
PWE
t
SD
t
HD
t
HZWE
(3)
t
LZWE
(3)
Notes:
Address Hold from Write End
Address Setup Time
LB, UB
Valid to End of Write
WE
Pulse Width
Data Setup to Write End
Data Hold from Write End
WE
LOW to High-Z Output
WE
HIGH to Low-Z Output
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V, input pulse levels of 0.4V to 1.4V
and output loading specified in Figure 1.
2. The internal write time is defined by the overlap of
CS1
LOW, CS2 HIGH and
UB
or
LB,
and
WE
LOW. All signals must be in valid states to initiate a Write, but
any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the
write.
3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. E
06/08/05
9
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
