IS80C52
IS80C32
®
ISSI
The detail description of each bit is as follows:
IE:
Interrupt Enable Register. Bit Addressable.
PSW:
Program Status Word. Bit Addressable.
7
6
5
4
3
2
1
0
EA
—
ET2
ES
ET1 EX1 ET0 EX0
7
6
5
4
3
2
1
0
CY AC
F0
RS1 RS0
OV
—
P
Register Description:
EA
IE.7
Disable all interrupts. If EA=0, no
interrupt will be acknowledged. If
EA=1, each interrupt source is
individually enabled or disabled by
setting or clearing its enable bit.
Register Description:
CY
AC
F0
PSW.7
PSW.6
PSW.5
Carry flag.
Auxiliary carry flag.
Flag 0 available to the user for
general purpose.
—
IE.6
Not implemented, reserve for future
use.(5)
RS1 PSW.4
RS0 PSW.3
Register bank selector bit 1.(1)
Register bank selector bit 0.(1)
Overflow flag.
ET2 IE.5
ES IE.4
Enables or disables timer 2 overflow
interrupt.
OV
—
P
PSW.2
PSW.1
PSW.0
Usable as a general purpose flag
Enable or disable the serial port
interrupt.
Parity flag. Set/Clear by hardware each
instruction cycle to indicate an odd/even
number of “1” bits in the accumulator.
ET1 IE.3
Enable or disable the timer 1 overflow
interrupt.
Note:
EX1 IE.2
ET0 IE.1
Enable or disable external interrupt 1.
1. The value presented by RS0 and RS1 selects the corre-
sponding register bank.
Enable or disable the timer 0 overflow
interrupt.
RS1
RS0
Register Bank
Address
EX0 IE.0
Enable or disable external interrupt 0.
0
0
1
1
0
1
0
1
0
1
2
3
00H-07H
08H-0FH
10H-17H
18H-1FH
Note:
To use any of the interrupts in the 80C51 Family, the following
three steps must be taken:
1. Set the EA (enable all) bit in the IE register to 1.
2. Set the coresponding individual interrupt enable bit in the IE
register to 1.
3. Begin the interrupt service routine at the corresponding
Vector Address of that interrupt (see below).
PCON:
Power Control Register. Not Bit Addressable.
7
6
5
4
3
2
1
0
Interrupt Source
Vector Address
0003H
SMOD —
—
—
GF1 GF0
PD IDL
IE0
TF0
000BH
Register Description:
IE1
0013H
SMOD
Doublebaudratebit. IfTimer1isusedtogenerate
baud rate and SMOD=1, the baud rate is doubled
when the serial port is used in modes 1, 2, or 3.
Not implemented, reserve for future use.(1)
Not implemented, reserve for future use.(1)
Not implemented, reserve for future use.(1)
General purpose flag bit.
TF1
001BH
RI & TI
TF2 and EXF2
0023H
—
002BH
—
4. In addition, for external interrupts, pins INT0 and INT1 (P3.2
and P3.3) must be set to 1, and depending on whether the
interrupt is to be level or transition activated, bits IT0 or IT1
in the TCON register may need to be set to 0 or 1.
ITX = 0 level activated (X = 0, 1)
ITX = 1 transition activated
5. User software should not write 1s to reserved bits. These bits
may be used in future products to invoke new features.
—
GF1
GF0
PD
General purpose flag bit.
Power-downbit.Settingthisbitactivatespower-
down operation in the IS80C52/32.
IDL
Idlemodebit. Settingthisbitactivatesidlemode
operation in the IS80C52/32. If 1s are written to
PD and IDL at the same time, PD takes
precedence.
Note:
1. User software should not write 1s to reserved bits. These bits
may be used in future products to invoke new features.
Integrated Silicon Solution, Inc. — 1-800-379-4774
MC004-1D
11/19/98
11
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
