CPC7524
INTEGRATED
C
IRCUITS
D
IVISION
3. Functional Description
3.1 Introduction
To protect against a high voltage fault in excess of the
CPC7524’s maximum voltage rating, use of an
over-voltage protector is required. The protector must
The CPC7524 High Voltage Quad Analog Switch
Array has four independent symmetrical switches
providing 16 unique operating states. These
operational states and the logical behavior of the
device are shown in the tables given in “Truth
Tables” on page 8. Switch organization consists of
two channels each having a pair of switches. Within
each channel there is a single LATCH input and a
single Temperature Shutdown circuit shared by the
switch pair. Other than these two shared circuits the
performance of each switch within a channel is
independent of the other. As there is no shared
circuitry between the channels, the switches of one
channel are completely independent of the other
channel. Switch utilization under normal operating
conditions allows the switches to be used in any
combination. In designs where the switches will be
required to carry high load currents or operate in
higher temperature environments the thermal
specifications should be reviewed.
limit the voltage seen at the S and S terminals to a
xA
xB
level below the switches maximum breakdown
voltage. With proper selection of the protector, telecom
applications using the CPC7524 will meet all relevant
ITU, LSSGR, TIA/EIA and IEC protection
requirements.
Operating from a +3.3V supply the CPC7524 has
extremely low power consumption.
3.2 Under-Voltage Switch Lock-Out Circuitry
Smart logic in the CPC7524 provides for switch state
control during both power up and power loss
transitions to prevent undesired connections to high
voltage networks. An internal detector evaluates the
V
supply to determine when to de-assert the
DD
under-voltage switch lock-out circuitry with a rising
, and when to assert the under-voltage switch
V
Solid-state switch construction of the CPC7524 offers
clean, bounce-free switching with simple logic input
control to provide access to high voltage interfaces
without the impulse noise generated by traditional
electromechanical switching techniques. Simple logic
input control eliminates the additional driver circuitry
required by traditional techniques.
DD
lock-out circuitry with a falling V . Any time
DD
unsatisfactory low V conditions exist, the lock-out
DD
circuit overrides user switch control by blocking the
external information at the input pins, and conditioning
internal switch commands to the All-Off state. Upon
restoration of V , the switches will remain off until the
DD
LATCH input is pulled low with proper conditioning of
The low on-resistance (R ) symmetrical linear
x
ON
the IN inputs.
switches are configured as matched pairs, SW1/SW2
and SW3/SW4, for improved performance when
differential access is required. Their symmetrical
construction provides an additional degree of design
flexibility allowing either side of the switch to be
connected to the high voltage network.
x
The rising V lock-out release threshold is internally
DD
set to ensure all internal logic is properly biased and
functional before accepting external switch commands
from the inputs to control the switch states. For a
falling V event, the lock-out threshold is set to
DD
Integrated into the CPC7524 switches are active
current limiting and thermal shutdown mechanisms to
provide protection for the electronics being connected
to the high voltage network during a fault condition.
High frequency positive and negative transient
currents such as lightning are reduced by the current
limiting circuitry. Protection from prolonged low
frequency fault events and DC currents, also reduced
by the current limiting circuitry, is supplemented by
thermal shutdown circuits.
assure proper logic and switch behavior up to the
moment the switches are forced off and external
inputs are suppressed.
3.3 Switch Logic
3.3.1 Data Latch
The CPC7524 has two integrated transparent data
latches. The latch-enable operation is controlled by
logic input levels at the LATCH pins. Data input to the
x
latch is via the IN input pins while the outputs of the
x
data latch are internal nodes used for state control.
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