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IDT723643L15PF 参数 Datasheet PDF下载

IDT723643L15PF图片预览
型号: IDT723643L15PF
PDF下载: 下载PDF文件 查看货源
内容描述: CMOS总线匹配SyncFIFOTM 256× 36 , 512× 36 , 1024× 36 [CMOS BUS-MATCHING SyncFIFOTM 256 x 36, 512 x 36, 1,024 x 36]
分类和应用: 配套器件先进先出芯片
文件页数/大小: 28 页 / 283 K
品牌: JGD [ JINAN GUDE ELECTRONIC DEVICE ]
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CMOS BUS-MATCHING SyncFIFO
TM
256 x 36, 512 x 36, 1,024 x 36
.EATURES:
IDT723623
IDT723633
IDT723643
Memory storage capacity:
IDT723623 – 256 x 36
IDT723633 – 512 x 36
IDT723643 – 1,024 x 36
Clocked FIFO buffering data from Port A to Port B
Clock frequencies up to 83 MHz (8 ns access time)
IDT Standard timing (using
EF
and
FF)
or First Word Fall
Through Timing (using OR and IR flag functions)
Programmable Almost-Empty and Almost-Full flags; each has
three default offsets (8, 16 and 64)
Serial or parallel programming of partial flags
Port B bus sizing of 36 bits (long word), 18 bits (word) and 9 bits
(byte)
Big- or Little-Endian format for word and byte bus sizes
Reset clears data and configures FIFO, Partial Reset clears data
but retains configuration settings
Mailbox bypass registers for each FIFO
Free-running CLKA and CLKB may be asynchronous or
coincident (simultaneous reading and writing of data on a single
clock edge is permitted)
Easily expandable in width and depth
Auto power down minimizes power dissipation
Available in a space-saving 128-pin Thin Quad Flatpack (TQFP)
Industrial temperature range (–40°C to +85°C) is available
°
°
DESCRIPTION:
The IDT723623/723633/723643 are monolithic, high-speed, low-power,
CMOS unidirectional Synchronous (clocked) FIFO memories which support
clock frequencies up to 83 MHz and have read access times as fast as 8 ns.
.UNCTIONAL BLOCK DIAGRAM
MBF1
Mail 1
Register
Port-A
Control
Logic
CLKA
CSA
W/RA
ENA
MBA
RS1
RS2
PRS
Bus-
Matching
Input
Register
Output
Register
FIFO1
Mail1,
Mail2,
Reset
Logic
36
36
RAM ARRAY
256 x 36
512 x 36
1,024 x 36
36
36
A
0
-A
35
Write
Pointer
Read
Pointer
B
0
-B
35
FF/IR
AF
Status Flag
Logic
EF/OR
AE
36
36
SPM
FS0/SD
FS1/SEN
Programmable Flag
Offset Registers
10
Timing
Mode
Port-B
Control
Logic
Mail 2
Register
MBF2
IDT, the IDT logo are registered trademarks of Integrated Device Technology, Inc. SyncFIFO is a trademark of Integrated Device Technology, Inc.
FWFT
CLKB
CSB
W/RB
ENB
MBB
BE
BM
SIZE
3269 drw01
COMMERCIAL TEMPERATURE RANGE
1
2001 Integrated Device Technology, Inc.
All rights reserved. Product specifications subject to change without notice.
AUGUST 2001
DSC-3269/2