IRFR9120, IRFU9120, SiHFR9120, SiHFU9120
Peak Diode Recovery dV/dt Test Circuit
+
P.W.
Period
Ripple
≤
5
%
D.U.T.
Circuit layout considerations
•
Low stray inductance
•
Ground plane
•
Low leakage inductance
current transformer
R
G
Compliment
N-Channel
of D.U.T. for driver
Driver gate drive
D=
D.U.T. I
SD
waveform
Reverse
recovery
current
Body diode forward
current
dI/dt
D.U.T.
V
DS
waveform
Diode recovery
dV/dt
Re-applied
voltage
Inductor current
Body diode forward drop
*
V
GS
= - 5
V
for logic level and - 3
V
drive devices
Fig. 14 - For P-Channel
-
+
-
+
-
•
dV/dt controlled
by
R
G
•
I
SD
controlled
by
duty factor "D"
•
D.U.T. - device
under
test
+
-
V
DD
P.W.
Period
V
GS
= - 10
V*
V
DD
I
SD
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