ML145040, ML145041
PIN DESCRIPTIONS
LANSDALE Semiconductor, Inc.
DIGITAL INPUTS AND OUTPUTS
CS (Pin 15)
Active–low chip select input. CS provides three–state control
of Dout. CS at a high logic level forces Dout to a high–imped-
ance state. IN addition, the device recognizes the falling edge
of CS as a serial interface reset to provide synchronization
between the MPU and the A/D converter’s serial data stream.
To prevent a spurious reset from occurring due to noise on the
CS input, a delay circuit has been included such that a CS sig-
nal of duration
≤1
A/D CLK period (ML145040) or
≤500
ns
(ML145041) is ignored. A valid CS signal is acknowledged
when the duration is
≥3
A/D CLK periods (ML145040) or
≥3
µs
(ML145041)
CAUTION
A reset aborts a conversion sequence, therefore
high–to–low transitions on CS must be avoided dur-
ing the conversion sequence.
Dout (Pin 16)
Serial data output of the A/D conversion result. The 8–bit
serial data stream begins with the most significant bit and is
shifted out on the high–to–low transition of SCLK. Dout is a
three–state output as controlled by CS. However, Dout is
forced into a high–impedance state after the eighth SCLK,
independent of the state of CS. See Figures 9, 10, 11, or 12.
Din (Pin 17)
Serial data input. The 4–bit serial data stream begins with the
most significant address bit of the analog mux and is shifted in
on the low–to–high transition of SCLK.
SCLK (Pin 18)
Serial data clock. THe serial data register is completely stat-
ic, allowing SCLK rates down to DC in a continuos or inter-
mittent mode. SCLK need not be synchronous to the A/D CLK
(ML145040) or the internal clock (ML145041). Eight SCLK
cycles are required for each simultaneous data transfer, the
low–to–high transition shifting in the new address and the
high–to–low transition shifting out the previous conversion
result. The address is acquired during the first four SCLK
cycles, with the interval produced by the remaining four cycles
being used to begin charging the on–chip sample–and–hold
capacitors. After the eighth SCLK, the SCLK input is inhibited
(on–chip) until the conversion is complete.
A/D CLK (Pin 18, ML145040 only)
A/D clock input. This pin clocks the dynamic A/D conver-
sion sequence, and may be asynchronous and unrelated to
SCLK. The signal must be free running, and may be obtained
from the MPU system clock. Deviations from a 50% duty
cycle can be tolerated if each half period is > 238 ns.
EOC (Pin 19, ML145041 only)
End–of–conversion output. EOC goes low on the negative
edge of the eighth SCLK. The low–to–high transition of EOC
indicates the A/D conversion is complete and the data is ready
for transfer.
ANALOG INPUTS AND TEST MODE
AN0 through AN10 (Pins 1-9, 11, 12)
Analog multiplexer inputs. The input AN0 is addressed by
loading $0 into the serial data input, Din. AN1 is addressed by
$1, AN2 by $2…AN10 via $A. The mux features a
break–before–make switching structure to minimize noise
injection into the analog inputs. The source impedance driving
these inputs must be
≤
10 kΩ. NOTE: $B addresses an on–chip
test voltage of (Vref + VAG)/2, and produces an output of $80
if the converter is functioning properly. However, a ± 1 LSB
deviation from $80 occurs in the presence of sufficient system
noise (external to the chip) on VDD, VSS, Vref or VAG.
POWER AND REFERENCE PINS
VSS and VDD (Pins 10 and 20)
Device supply pins. VSS is normally connected to digital
ground; VDD is connected to a positive digital supply voltage.
VDD – VSS variations over the range of 4.5 to 5.5 volts do not
affect the A/D accuracy. Excessive inductance in the VDD or
VSS lines as on automatic test equipment, may cause A/D off-
sets >
1
/
2
LSB.
VAG and Vref (Pins 13 and 14)
Analog reference voltage pins which determine the lower and
upper boundary of the A/D conversion. Analog input voltages
≥
Vref produce an output of $FF and input voltages
≤
VAG pro-
duce an output of $00. CAUTION: THe analog input voltage
must be
≥
VSS and
≤
VDD. The A/D conversion result is ratio-
metric to Vref – VAG as shown by the formula:
Vref and VAG should be as noise–free as possible to avoid
degradation of the A/D conversion. Noise on either of these
pins will couple 1:1 to the analog input signal i.e. a 20 mV
change in Vref can cause a 20 mV error in the conversion
result. Ideally Vref and VAG should be single-point connected
to the voltage supply driving the system’s transducers.
Page 6 of 12
www.lansdale.com
Issue A
LANSDALE [ LANSDALE SEMICONDUCTOR INC. ]
