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D9 – MSB
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
LOW
LEVEL
HIGH
IMPEDANCE
1
SAMPLE ANALOG INPUT
A3
A2
A1
A0
NOTE
2
A3
SHIFT IN NEW MUX ADDRESS,
SIMULTANEOUSLY SHIFT OUT PREVIOUS CONVERSION VALUE
INITIALIZE
A/D
CONVERSION
INTERVAL
RE-INITIALIZE
CS
ML145050, ML145051
D out
SCLK
D in
EOC
Figure 13. Timing for 11- to 16-Clock Transfer Using CS* (Serial Transfer Interval Longer Than Conversion)
CS
MUST BE HIGH ON POWER UP
www.lansdale.com
D7
D6
D5
D4
D3
D2
D1
D0
SAMPLE ANALOG INPUT
A1
A0
SHIFT IN NEW MUX ADDRESS,
SIMULTANEOUSLY SHIFT OUT PREVIOUS CONVERSION VALUE
A/D CONVERSION
INTERVAL
D out
D9 – MSB
D8
LOW LEVEL
D9
SCLK
NOTE 2
A3
1
D in
A3
A2
MSB
EOC
INITIALIZE
Figure 14. Timing for 16-Clock Transfer Not Using CS* (Serial Transfer Interval Longer Than Conversion)
LANSDALE Semiconductor, Inc.
NOTES:
D9, D8, D7, . . . , D0 = the result of the previous A/D conversion.
A3, A2, A1, A0 = the mux address for the next A/D conversion.
*NOTES:
1. This figure illustrates the behavior of the ML145051. The ML145050 behaves identically except there is no EOC signal and the conversion time is 44 ADCLK cycles (user-controlled time).
2. The 11th SCLK rising edge must occur before the conversion is complete. Otherwise the serial port is thrown out of sync with the microprocessor for the remainder of the transfer.
Issue B
LANSDALE [ LANSDALE SEMICONDUCTOR INC. ]
