ML13156
LANSDALE Semiconductor, Inc.
QUADRATURE DETECTOR
The quadrature detector is a doubly balanced four quadrant
multiplier with an internal 5.0 pF quadrature capacitor to cou-
ple the IF signal to the external parallel RLC resonant circuit
that provides the 90 degree phase shift and drives the quadra-
ture detector. A single pin (Pin 13) provides for the external
LC parallel resonant network and the internal connection to
the quadrature detector.
The bandwidth of the detector allows for recovery of relative-
ly high data rate modulation. The recovered signal is convert-
ed from differential to single ended through a push–pull
NPN/PNP output stage. Variation in recovered audio output
voltage with supply voltage is very small (see Figure 13). The
output drive capability is approximately ±9.0
µA
for a fre-
quency deviation of ±75 kHz and 1.0 kHz modulating fre-
quency (see Application Circuit)
DATA SLICER
The data slicer input (Pin 15) is self centering around 1.1 V
with clamping occurring at 1.1 ± 0.5 Vbe Vdc. It is designed
to square up the data signal. Figure 14 shows a detailed
schematic of the data slicer.
The Voltage Regulator sets up to 1.1 Vdc on the base of Q12,
the Differential Input Amplifier. There is a potential of 1.0
Vbe on the base–collector of transistor diode Q11 and 2.0
Vbe on the base–collector of Q10. This sets up a 1.5 Vbe
(~1.1 Vdc) on the node between the 36 kΩ resistors which is
connected to the base of Q12. The differential output of the
data slicer Q12 and Q13 is converted to a single–ended out-
put by the Driver Circuit. Additional circuitry, not shown in
Figure 14, tends to keep the data slicer input centered at 1.1
Vdc as input signal levels vary.
The Input Diode Clamp Circuit provides the clamping at 1.0
Vbe (0.75 Vdc) and 2.0 Vbe (1.45 Vdc). Transistor diodes Q7
and Q8 are on , thus, providing a 2.0 Vbe potential at the base
of Q1. Also, the voltage regulator circuit provides a potential
of 2.0 Vbe on the base of Q3 and 1.0 Vbe on the emitter of
Q3 and Q2. When the data slicer input (Pin 15) is pulled up,
Q1 turns off; Q2 turns on, thereby clamping the input at 2.0
Vbe. On the other hand, when Pin 15 is pulled down, Q1
turns on; Q2 turns off, thereby clamping the input at 1.0 Vbe.
The recovered data signal from the quadrature detector is ac
coupled to the data slicer via an input coupling capacitor. The
size of the capacitor and the nature of the data signal deter-
mine how faithfully the data slicer shapes up the recovered
signal. The time constant is short for large peak to peak volt-
age swings or when there is a change in dc level at the detec-
tor output. For small signal or for continuous bits of the same
polarity which drift close to the threshold voltage, the time
constant is longer. When centered there is no input current
allowed, which is to say, that the input looks high in imped-
ance.
Another unique feature of the data slicer is that it responds to
various logic levels applied to the Data Slicer Hold Control
pin (Pin 18). Figure 15 illustrates how the input and output
currents under “no hold” condition relate to the input voltage.
Figure 16 shows how the input current and input voltage
relate to the both the “no hold” and “hold” condition.
The Hold control (Pin 18) does three separate tasks:
1) With Pin 18 at 1.0 Vbe or greater, the output is shut off
(sets high). Q19 turns on which shunts the base drive
from Q20, thereby turning the output off.
2) With Pin 18 at 2.0 Vbe or greater, internal clamping diodes
are open circuited and the comparator input is shut off and
effectively open circuited. This is accomplished by turning
off the current source to emitters of the input differential
amplifier, thus, the input differential amplifier is shut off.
3) When the input is shut off, it allows the input capacitor to
hold its charge during transmit to improve recovery at the
beginning of the next receive period. When it is turned on,
it allows for very fast charging of the input capacitor for
quick recovery of new tuning or data average. The above
features are very desirable in a TDD digital FM system.
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