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D9 – MSB
D8
D9
D7
D6
D5
D4
D3
D2
D1
D0
LOW
LEVEL
HIGH
IMPEDANCE
1
SAMPLE ANALOG INPUT
A3
A2
A1
A0
A3
SHIFT IN NEW MUX ADDRESS,
SIMULTANEOUSLY SHIFT OUT PREVIOUS CONVERSION VALUE
A/D CONVERSION
INTERVAL
RE-INITIALIZE
D7
D6
D5
D4
D3
D2
D1
D0
LOW LEVEL
D9
1
SAMPLE ANALOG INPUT
A1
A0
A3
SHIFT IN NEW MUX ADDRESS,
SIMULTANEOUSLY SHIFT OUT PREVIOUS CONVERSION VALUE
A/D CONVERSION INTERVAL
CS
ML145050, ML145051
D out
SCLK
D in
EOC
INITIALIZE
Figure 11. Timing for 11- to 16-Clock Transfer Using CS* (Serial Transfer Interval Shorter than Conversion)
CS
MUST BE HIGH ON POWER UP
www.lansdale.com
D out
D9 – MSB
D8
SCLK
D in
A3
A2
MSB
EOC
INITIALIZE
Figure 12. Timing for 16-Clock Transfer Not Using CS* (Serial Transfer Interval Shorter Than Conversion)
LANSDALE Semiconductor, Inc.
NOTES:
D9, D8, D7, . . . , D0 = the result of the previous A/D conversion.
A3, A2, A1, A0 = the mux address for the next A/D conversion.
*This figure illustrates the behavior of the ML145051. The ML145050 behaves identically except there is no EOC signal and the conversion time is 44 ADCLK cycles (user-controlled time).
Issue B
LANSDALE [ LANSDALE SEMICONDUCTOR INC. ]
