ML145145
4–Bit Data Bus Input PLL
Frequency Synthesizer
INTERFACES WITH SINGLE–MODULUS PRESCALERS
Legacy Device:
Motorola MC145145-2
The ML145145 is programmed by a 4–bit input, with
strobe and address lines. The device features consist of a
reference oscillator, 12–bit programmable reference
divider, digital phase detector, 14–bit programmable
divide–by–N counter, and the necessary latch circuitry for
accepting the 4–bit input data.
• Operating Temperature Range: TA – 40 to 85°C
• Low Power Consumption Through the Use of CMOS
Technology
• 3.0 to 9.0 V Supply Range
• Single Modulus 4–Bit Data Bus Programming
• ÷N Range = 3 to 16,383, ÷R Range = 3 to 4,095
• “Linearized” Digital Phase Detector Enhances
Transfer Function Linearity
• Two Error Signal Options:
Single–Ended (Three–State)
Double–Ended
P DIP 18 = VP
PLASTIC DIP
CASE 707
18
1
20
SOG 20 = -6P
SOG PACKAGE
CASE 751D
1
CROSS REFERENCE/ORDERING INFORMATION
MOTOROLA
LANSDALE
PACKAGE
P DIP 18
MC145145P1
ML145145VP
SOG 20
MC145145DW2 ML145145-6P
Note:
Lansdale lead free (Pb) product, as it
becomes available, will be identified by a part
number prefix change from
ML
to
MLE.
PIN ASSIGNMENTS
PLASTIC DIP
D1
D0
fin
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
D2
D3
REFout
φ
R
φ
V
LD
PDout
ST
A2
BLOCK DIAGRAM
REFout
VSS
VDD
OSCin
OSCout
OSCin
OSCout
12–BIT R COUNTER
LATCH 4
LATCH 5
LATCH 6
LOCK
DETECT
LD
A0
A1
SOG PACKAGE
D1
D0
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
D2
D3
REFout
φ
R
φ
V
LD
PDout
ST
A2
NC
D0
D1
D2
D3
A0
A1
A2
ST
fR
LATCH
CONTROL
CIRCUITRY
fV
LATCHES
PHASE
DETECTOR
A
PDout
NC
fin
VSS
VDD
LATCH 0
fin
LATCH 1
LATCH 2
L3
PHASE
DETECTOR
B
φ
V
φ
R
OSCin
OSCout
A0
A1
14–BIT N COUNTER
NC = NO CONNECTION
Page 1 of 12
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Issue b
B
LANSDALE [ LANSDALE SEMICONDUCTOR INC. ]
