LANSDALE Semiconductor, Inc.
ML145554, ML145557, ML145564, ML145567
complementary outputs. The output of the second amplifier may be
internally connected to the input of the transmit anti–aliasing filter by
bringing the ANLB pin high. The power amplifiers can drive unbal-
anced 300
Ω
loads or a balanced 600
Ω
load; they may be powered
down independent of the rest of the chip by tying the VPI pin to
VBB.
MASTER CLOCKS
Since the codec–filter design has a single DAC architecture, only
one master clock is used. In normal operation (both frame syncs
clocking), the MCLKX is used as the master clock, regardless of
whether the MCLKR/PDN pin is clocking or low. The same is true if
the part is in transmit half–channel mode (FSX clocking, FSR held
low). But if the codec–filter is in the receive half–channel mode, with
FSR clocking and FSX held low, MCLKR is used for the internal
master clock if it is clocking; if MCLKR is low, then MCLKX is still
used for the internal master clock. Since only one of the master
clocks isused at any given time, they need not be synchronous.
The master clock frequency must be 1.536 MHz, 1.544 MHz, or
2.048 MHz. The frequency that the codec–filter expects depends
upon whether the part is a Mu–Law or an A–Law part, and on the
state of the BCLKR/CLKSEL pin.The allowable options are shown
In Table 1. When a level (rather than a clock) is provided for
BCLKR/CLKSEL, BCLKX is used as the bit clock for both transmit
and receive.
Table 1. Master Clock Frequency Determination
Master Clock Frequency Expected
BCLKR/CLKSEL
Clocked, 1, or Open
0
ML145554/64
1.536 MHz
1.544 MHz
2.048 MHz
ML145557/67
2.048 MHz
1.536 MHz
1.544 MHz
high, the sign bit appears at the DX output. The next seven rising
edges of BCLKX clock out the remaining seven bits of the PCM
word. The DX and TSX outputs return to a high impedance state on
the falling edge of the eighth bit clock or the falling edge of FSX,
whichever comes later. The receive PCM word is clocked into DR on
the eight falling BCLKR edges following an FSR rising edge.
For Short Frame Sync operation, the frame sync pulses must be
one bit clock period long. On the first BCLKX rising edge after the
falling edge of BCLKX has latched FSX high, the DX and TSX out-
puts are enabled and the sign bit is presented on DX. The next seven
rising edges of BCLKX clock out the remaining seven bits of the
PCM word; on the eighth BCLKX falling edge, the DX and TSX
outputs return to a high impedance state. On the second falling
BCLKR edge following an FSR rising edge, the receive sign bit is
clocked into DR. The next seven BCLKR falling edges clock in the
remaining seven bits of the receive PCM word.
Table 2 shows the coding format of the transmit and receive PCM
words.
HALF–CHANNEL MODES
In addition to the normal full–duplex operating mode, these
codec–filters can operate in both transmit and receive half–channel
modes. Transmit half–channel mode is entered by holding FSR low.
The VFRO output goes to analog ground but remains in a low imped-
ance state (to facilitate a hybrid interface); PCM data at DR is
ignored. Holding FSX low while clocking FSR puts these devices in
the receive half–channel mode. In this state, the transmit input oper-
ational amplifier continues to operate, but the rest of the transmit cir-
cuitry is disabled; the DX and TSX outputs remain in a high imped-
ance state. MCLKR is used as the internal master clock if it is clock-
ing. If MCLKR is not clocking, then MCLKX is used for the internal
master clock, but in that case it should be synchronous with FSR. If
BCLKR is not clocking, BCLKX will be used for the receive data,
just as in the full–channel operating mode. In receive half–channel
mode only, the length ofthe FSR pulse is used to determine whether
Short Frame Sync or Long Frame Sync timing is used at DR.
POWER–DOWN
FRAME SYNCS AND DIGITAL I/O
These codec–filters can accommodate both of the industry standard
timing formats. The Long Frame Sync mode isused by Lansdale’s
ML145500 family of codec–filters and the UDLT family of digital
loop transceivers. The Short Frame Sync mode is compatible with the
IDL (Interchip Digital Link) serial format used in Motorola and
Lansdale’s ISDN family and by other companies in their telecommu-
nication devices. These codec–filters use the length of the transmit
frame sync (FSX) to determine the timing format for both transmit
and receive unless the part is operating in the receive half–channel
mode.
In the Long Frame Sync mode, the frame sync pulses must be at
least three bit clock periods long. The DX and TSX outputs are
enabled by the logical ANDing of FSX and BCLKX; when both are
Mu–Law (ML145554/64)
Level
+ Full Scale
+ Zero
– Zero
– Full Scale
Sign Bit
1
1
0
0
Chord Bits
000
111
111
000
Holding both FSX and FSR low causes the part to go into the
power–down state. Power–down occurs approximately 2 ms after the
last frame sync pulse is received. An alternative way to put these
devices in power–down is to hold the MCLKR/PDN pin high. When
the chip is powered down, the DX, TSX, and GSX outputs are high
impedance, the VFRO, VPO–, and VPO+ operational amplifiers are
biased with a trickle current so that their respective outputs remain
stable at analog ground. To return the chip to the power–up state,
MCLKR/PDN must be low or clocking and at least one of the frame
sync pulses must be present. The DX and TSX outputs will remain in
a high–impedance state until the second FSX pulse after power–up.
Table 2. PCM Data Format
A–Law (ML145557/67)
Sign Bit
1
1
0
0
Chord Bits
010
101
101
010
Step Bits
1010
0101
0101
1010
0000
1111
1111
0000
Step Bits
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