ML4344_4044
Phase Frequency Detector
This device contains two digital phase detectors and a charge
pump circuit which converts MTTL inputs to a dc voltage level
for use in frequency discrimination and phase–locked–loop
applications.
The two phase detectors have common inputs. Phase–frequen-
cy detector 1 is locked in (indicated by both outputs high) when
the negative transitions of the variable input (V1) and reference
input (R1) are equal in frequency and phase. If the variable input
is lower in frequency or lags in phase, the U1 (up) output goes
low; conversely the D1 (down) output goes low when the vari-
able input is higher in frequency or leads the reference input in
phase. It is important to note that the duty cycles of the variable
input and the reference input are not important since negative
transitions control system operation.
Phase detector 2, on the other hand, is locked in when the vari-
able input phase lags the reference phase th 90º (indicated by the
U2 and D2 outputs alternately going low with equal pulse
widths). If the variable input phase lags by more than 90º, U2
will remain low longer than D2, and conversely, if the variable
input phase lags the reference phase by less than 90º, D2
remains low longer. In this phase detector the variable input and
the reference must have 50% duty cycles.
The charge pump accepts the phase detector outputs (U1 or U2
applied to PU, and D1 or D2 applied to PD) and converts them
to fixed amplitude positive and negative pulses at the UF and DT
outputs respectively. These pulses are applied to a lag-lead active
filter, which incorporates external components, as well as the
amplifier provided in the MC4344/4044 circuit. The filter pro-
vides a dc voltage proportional to the phase error.
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