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GAL20V8B-25LP 参数 Datasheet PDF下载

GAL20V8B-25LP图片预览
型号: GAL20V8B-25LP
PDF下载: 下载PDF文件 查看货源
内容描述: 高性能E2CMOS PLD通用阵列Logic⑩ [High Performance E2CMOS PLD Generic Array Logic⑩]
分类和应用: 可编程逻辑器件光电二极管输入元件时钟
文件页数/大小: 25 页 / 578 K
品牌: LATTICE [ LATTICE SEMICONDUCTOR ]
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Specifications
GAL20V8
Complex Mode
In the Complex mode, macrocells are configured as output only or
I/O functions.
Architecture configurations available in this mode are similar to the
common 20L8 and 20P8 devices with programmable polarity in
each macrocell.
Up to six I/Os are possible in this mode. Dedicated inputs or outputs
can be implemented as subsets of the I/O function. The two outer
most macrocells (pins 15 & 22) do not have input capability. De-
signs requiring eight I/Os can be implemented in the Registered
mode.
All macrocells have seven product terms per output. One product
term is used for programmable output enable control. Pins 1 and
13 are always available as data inputs into the AND array.
The JEDEC fuse numbers including the UES fuses and PTD fuses
are shown on the logic diagram on the following page.
Select devices have been discontinued.
See Ordering Information section for product status.
Combinatorial I/O Configuration for Complex Mode
- SYN=1.
- AC0=1.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1=1.
- Pin 16 through Pin 21 are configured to this function.
XOR
Combinatorial Output Configuration for Complex Mode
- SYN=1.
- AC0=1.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1=1.
- Pin 15 and Pin 22 are configured to this function.
XOR
Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.
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