GAL20XV10B-15LP 参数 Datasheet PDF下载

GAL20XV10

High-Speed E

2

CMOS PLD

Generic Array Logic™

Features

• HIGH PERFORMANCE E

2

CMOS

®

TECHNOLOGY

— 10 ns Maximum Propagation Delay

— Fmax = 100 MHz

— 7 ns Maximum from Clock Input to Data Output

— TTL Compatible 16 mA Outputs

— UltraMOS

®

Advanced CMOS Technology

• 50% to 75% REDUCTION IN POWER FROM BIPOLAR

— 90mA Maximum Icc

— 75mA Typical Icc

• ACTIVE PULL-UPS ON ALL PINS

• E

2

CELL TECHNOLOGY

— Reconfigurable Logic

— Reprogrammable Cells

— 100% Tested/100% Yields

— High Speed Electrical Erasure (<100 ms)

— 20 Year Data Retention

• TEN OUTPUT LOGIC MACROCELLS

— XOR Gate Capability on all Outputs

— Full Function and Parametric Compatibility with

PAL12L10, 20L10, 20X10, 20X8, 20X4

— Registered or Combinatorial with Polarity

• PRELOAD AND POWER-ON RESET OF ALL REGISTERS

• APPLICATIONS INCLUDE:

— High Speed Counters

— Graphics Processing

— Comparators

• ELECTRONIC SIGNATURE FOR IDENTIFICATION

Functional Block Diagram

I/CLK

4

OLMC

I/O/Q

I

4

OLMC

I

4

I/O/Q

I

OLMC

I/O/Q

PROGRAMMABLE

AND-ARRAY

(40 X 40)

4

OLMC

I

I/O/Q

4

OLMC

I

I/O/Q

I

4

OLMC

I/O/Q

I

4

OLMC

I/O/Q

I

4

OLMC

I/O/Q

I

4

OLMC

I/O/Q

I

4

OLMC

I/O/Q

Description

The GAL20XV10 combines a high performance CMOS process

with electrically erasable (E

2

) floating gate technology to provide

the highest speed Exclusive-OR PLD available in the market. At

90mA maximum Icc (75mA typical Icc), the GAL20XV10 provides

a substantial savings in power when compared to bipolar counter-

parts. E

2

CMOS technology offers high speed (<100ms) erase

times providing the ability to reprogram, reconfigure or test the de-

vices quickly and efficiently.

The generic architecture provides maximum design flexibility by

allowing the Output Logic Macrocell (OLMC) to be configured by

the user. An important subset of the many architecture configu-

rations possible with the GAL20XV10 are the PAL

®

architectures

listed in the macrocell description section of this document. The

GAL20XV10 is capable of emulating these PAL architectures with

full function and parametric compatibility.

Unique test circuitry and reprogrammable cells allow complete AC,

DC, and functional testing during manufacturing. As a result, Lattice

Semiconductor delivers 100% field programmability and function-

ality of all GAL products. In addition, 100 erase/write cycles and

data retention in excess of 20 years are specified.

I/OE

Pin Configuration

DIP

PLCC

I/CLK

I/CLK

I/O/Q

Vcc

I/O/Q

1

24

Vcc

I/O/Q

I/O/Q

I

I

25

I/O/Q

I/O/Q

I

I

NC

4

I

I

I

NC

I

I

I

11

12

I

I

2

28

26

5

I

I

I

I

I

I

I

I

GND

12

6

GAL

20XV10

I/O/Q

I/O/Q

I/O/Q

7

GAL20XV10

Top View

14

GND

NC

23

I/O/Q

NC

9

21

I/O/Q

I/O/Q

18

I/O/Q

I/O/Q

I/O/Q

I/O/Q

I/O/Q

19

16

I/O/Q

I/OE

I/O/Q

18

I/O/Q

13

I/OE

Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject

to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 681-0118; 1-888-ISP-PLDS; FAX (503) 681-3037; http://www.latticesemi.com

July 1997

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