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GAL20V8B-10LPI 参数 Datasheet PDF下载

GAL20V8B-10LPI图片预览
型号: GAL20V8B-10LPI
PDF下载: 下载PDF文件 查看货源
内容描述: 高性能E2CMOS PLD通用阵列逻辑 [High Performance E2CMOS PLD Generic Array Logic]
分类和应用: 可编程逻辑器件光电二极管输入元件时钟
文件页数/大小: 23 页 / 309 K
品牌: LATTICE [ LATTICE SEMICONDUCTOR ]
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Specifications GAL20V8  
Complex Mode  
In the Complex mode, macrocells are configured as output only or signs requiring eight I/Os can be implemented in the Registered  
I/O functions. mode.  
Architecture configurations available in this mode are similar to the All macrocells have seven product terms per output. One product  
common 20L8 and 20P8 devices with programmable polarity in term is used for programmable output enable control. Pins 1 and  
each macrocell.  
13 are always available as data inputs into the AND array.  
Up to six I/Os are possible in this mode. Dedicated inputs or outputs The JEDEC fuse numbers including the UES fuses and PTD fuses  
can be implemented as subsets of the I/O function. The two outer are shown on the logic diagram on the following page.  
most macrocells (pins 15 & 22) do not have input capability. De-  
Combinatorial I/O Configuration for Complex Mode  
- SYN=1.  
- AC0=1.  
- XOR=0 defines Active Low Output.  
- XOR=1 defines Active High Output.  
- AC1=1.  
XOR  
- Pin 16 through Pin 21 are configured to this function.  
Combinatorial Output Configuration for Complex Mode  
- SYN=1.  
- AC0=1.  
- XOR=0 defines Active Low Output.  
- XOR=1 defines Active High Output.  
- AC1=1.  
XOR  
- Pin 15 and Pin 22 are configured to this function.  
Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.  
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