Specifications
GAL20RA10
f
max Descriptions
CLK
CLK
LOGIC
ARRAY
REGISTER
LOGIC
ARRAY
REGISTER
t
su
t
co
f
max with No Feedback
Note: fmax
with no feedback may be less
than 1/(twh +
twl).
This is to allow for a
clock duty cycle of other than 50%.
f
max with External Feedback 1/(
t
su+
t
co)
Note: fmax
with external feedback is cal-
culated from measured
tsu
and
tco.
Switching Test Conditions
Input Pulse Levels
Input Rise and
Fall Times
-7/-10
-15/-20/-30
GND to 3.0V
2ns 10% – 90%
3ns 10% – 90%
1.5V
1.5V
See Figure
FROM OUTPUT (O/Q)
UNDER TEST
TEST POINT
R
1
+5V
Input Timing Reference Levels
Output Timing Reference Levels
Output Load
3-state levels are measured 0.5V from steady-state active
level.
R
2
C
L
*
Output Load Conditions (see figure)
Test Condition
A
B
C
Active High
Active Low
Active High
Active Low
R
1
470Ω
∞
470Ω
∞
470Ω
R
2
390Ω
390Ω
390Ω
390Ω
390Ω
C
L
50pF
50pF
50pF
5pF
5pF
*C
L
INCLUDES TEST FIXTURE AND PROBE CAPACITANCE
9
LATTICE [ LATTICE SEMICONDUCTOR ]
