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GAL22V10B-25LJ 参数 Datasheet PDF下载

GAL22V10B-25LJ图片预览
型号: GAL22V10B-25LJ
PDF下载: 下载PDF文件 查看货源
内容描述: 高性能E2CMOS PLD通用阵列逻辑 [High Performance E2CMOS PLD Generic Array Logic]
分类和应用:
文件页数/大小: 29 页 / 387 K
品牌: LATTICE [ LATTICE SEMICONDUCTOR ]
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Specifications
GAL22V10
GAL22V10
High Performance E
2
CMOS PLD
Generic Array Logic™
Features
• HIGH PERFORMANCE E
2
CMOS
®
TECHNOLOGY
— 4 ns Maximum Propagation Delay
— Fmax = 250 MHz
— 3.5 ns Maximum from Clock Input to Data Output
— UltraMOS
®
Advanced CMOS Technology
• ACTIVE PULL-UPS ON ALL PINS
I
Functional Block Diagram
I/CLK
RESET
8
OLMC
I/O/Q
I
10
OLMC
I/O/Q
• COMPATIBLE WITH STANDARD 22V10 DEVICES
— Fully Function/Fuse-Map/Parametric Compatible
with Bipolar and UVCMOS 22V10 Devices
• 50% to 75% REDUCTION IN POWER VERSUS BIPOLAR
— 90mA Typical Icc on Low Power Device
— 45mA Typical Icc on Quarter Power Device
• E
2
CELL TECHNOLOGY
— Reconfigurable Logic
— Reprogrammable Cells
— 100% Tested/100% Yields
— High Speed Electrical Erasure (<100ms)
— 20 Year Data Retention
• TEN OUTPUT LOGIC MACROCELLS
— Maximum Flexibility for Complex Logic Designs
• PRELOAD AND POWER-ON RESET OF REGISTERS
— 100% Functional Testability
• APPLICATIONS INCLUDE:
— DMA Control
— State Machine Control
— High Speed Graphics Processing
— Standard Logic Speed Upgrade
• ELECTRONIC SIGNATURE FOR IDENTIFICATION
ESCRIPTION
12
I
OLMC
I/O/Q
PROGRAMMABLE
AND-ARRAY
(132X44)
14
OLMC
I
I/O/Q
16
OLMC
I
I/O/Q
I
16
OLMC
I/O/Q
I
14
OLMC
I/O/Q
I
12
OLMC
I/O/Q
I
10
OLMC
I/O/Q
I
8
OLMC
I/O/Q
I
PRESET
Description
The GAL22V10, at 4ns maximum propagation delay time, combines
a high performance CMOS process with Electrically Erasable (E
2
)
floating gate technology to provide the highest performance avail-
able of any 22V10 device on the market. CMOS circuitry allows
the GAL22V10 to consume much less power when compared to
bipolar 22V10 devices. E
2
technology offers high speed (<100ms)
erase times, providing the ability to reprogram or reconfigure the
device quickly and efficiently.
The generic architecture provides maximum design flexibility by
allowing the Output Logic Macrocell (OLMC) to be configured by
the user. The GAL22V10 is fully function/fuse map/parametric com-
patible with standard bipolar and CMOS 22V10 devices.
Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacture. As a result, Lat-
tice Semiconductor delivers 100% field programmability and func-
tionality of all GAL products. In addition, 100 erase/write cycles and
data retention in excess of 20 years are specified.
Pin Configuration
DIP
PLCC
I/CLK
I/O/Q
I/O/Q
Vcc
I
I
NC
I/CLK
I
I
25
I/O/Q
I/O/Q
1
24
Vcc
I/O/Q
I/O/Q
4
I
I
I
NC
I
I
I
11
12
I
I
2
28
26
5
I
I
I
6
7
23
I/O/Q
NC
GAL
22V10
18
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
GAL22V10
9
Top View
14
GND
NC
21
I/O/Q
I/O/Q
I
I
I
I
I
GND
12
16
I
I/O/Q
19
18
I/O/Q
I/O/Q
13
I
Copyright © 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
August 2000
22v10_06
1