GAL6002
High Performance E
2
CMOS FPLA
Generic Array Logic™
Features
• HIGH PERFORMANCE E
2
CMOS
®
TECHNOLOGY
— 15ns Maximum Propagation Delay
— 75MHz Maximum Frequency
— 6.5ns Maximum Clock to Output Delay
— TTL Compatible 16mA Outputs
— UltraMOS
®
Advanced CMOS Technology
• ACTIVE PULL-UPS ON ALL PINS
• LOW POWER CMOS
— 90mA Typical Icc
• E
2
CELL TECHNOLOGY
— Reconfigurable Logic
— Reprogrammable Cells
— 100% Tested/100% Yields
— High Speed Electrical Erasure (<100ms)
— 20 Year Data Retention
• UNPRECEDENTED FUNCTIONAL DENSITY
— 78 x 64 x 36 FPLA Architecture
— 10 Output Logic Macrocells
— 8 Buried Logic Macrocells
— 20 Input and I/O Logic Macrocells
• HIGH-LEVEL DESIGN FLEXIBILITY
— Asynchronous or Synchronous Clocking
— Separate State Register and Input Clock Pins
— Functional Superset of Existing 24-pin PAL
®
and FPLA Devices
• APPLICATIONS INCLUDE:
— Sequencers
— State Machine Control
— Multiple PLD Device Integration
14
Functional Block Diagram
ICLK
INPUT
CLOCK
2
INPUTS
2-11
14
23
11
{
ILMC
RESET
IOLMC
AND
OUTPUT
ENABLE
D
E
23
OLMC
0
7
OR
D
BLMC
E
{
OUTPUTS
14 - 23
OCLK
OUTPUT
CLOCK
Macrocell Names
ILMC
BLMC
OLMC
INPUT LOGIC MACROCELL
BURIED LOGIC MACROCELL
OUTPUT LOGIC MACROCELL
IOLMC I/O LOGIC MACROCELL
PinNames
I
0
- I
10
ICLK
OCLK
INPUT
INPUT CLOCK
OUTPUT CLOCK
I/O/Q
V
CC
GND
BIDIRECTIONAL
POWER (+5V)
GROUND
Description
Having an FPLA architecture, the GAL6002 provides superior
flexibility in state-machine design. The GAL6002 offers the highest
degree of functional integration, flexibility, and speed currently
available in a 24-pin, 300-mil package. E
2
CMOS technology offers
high speed (<100ms) erase times, providing the ability to reprogram
or reconfigure the device quickly and efficiently.
The GAL6002 has 10 programmable Output Logic Macrocells
(OLMC) and 8 programmable Buried Logic Macrocells (BLMC). In
addition, there are 10 Input Logic Macrocells (ILMC) and 10
I/O Logic Macrocells (IOLMC). Two clock inputs are provided for
independent control of the input and output macrocells.
Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacturing. As a result, Lattice
Semiconductor delivers 100% field programmability and
functionality of all GAL products. In addition, 100 erase/write cycles
and data retention in excess of 20 years are specified.
Pin Configuration
PLCC
I/ICLK
I/ICLK
I/O/Q
I/O/Q
Vcc
NC
DIP
1
24
Vcc
I/O/Q
I
I
25
I/O/Q
I/O/Q
I
I
4
I
I
I
NC
I
I
I
11
12
9
7
5
2
28
26
I
I
I
I
I
I
I
I
GND
12
6
GAL
6002
18
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
13
OCLK
23
I/O/Q
NC
GAL6002
Top View
14
16
21
I/O/Q
I/O/Q
19
18
I/O/Q
I
I
OCLK
GND
NC
I/O/Q
Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
I/O/Q
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
July 1997
6002_02
1
LATTICE [ LATTICE SEMICONDUCTOR ]
