Lead-
Free
Package
Options
Available!
ispLSI 1016E
®
In-System Programmable High Density PLD
Functional Block Diagram
Features
• HIGH-DENSITY PROGRAMMABLE LOGIC
— 2000 PLD Gates
— 32 I/O Pins, Four Dedicated Inputs
— 96 Registers
— High-Speed Global Interconnect
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
• HIGH-PERFORMANCE E
2
CMOS
®
TECHNOLOGY
—
f
max
= 125 MHz Maximum Operating Frequency
—
t
pd
= 7.5 ns Propagation Delay
— TTL Compatible Inputs and Outputs
— Electrically Erasable and Reprogrammable
— Non-Volatile
— 100% Tested at Time of Manufacture
— Unused Product Term Shutdown Saves Power
• IN-SYSTEM PROGRAMMABLE
— In-System Programmable (ISP™) 5V Only
— Increased Manufacturing Yields, Reduced Time-to-
Market and Improved Product Quality
Output Routing Pool
A2
A3
A4
A5
A6
A7
Array
D
Global Routing Pool (GRP)
EW
ES
IG
D Q
Logic
D Q
B5
B4
B3
B2
B1
B0
GLB
D Q
CLK
— Reprogram Soldered Device for Faster Prototyping
— Enhanced Pin Locking Capability
— Three Dedicated Clock Input Pins
01
6E
• OFFERS THE EASE OF USE AND FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY
OF FIELD PROGRAMMABLE GATE ARRAYS
— Complete Programmable Device Can Combine Glue
Logic and Structured Designs
The ispLSI 1016E is a High Density Programmable Logic
Device containing 96 Registers, 32 Universal I/O pins,
four Dedicated Input pins, three Dedicated Clock Input
pins, one Global OE input pin and a Global Routing Pool
(GRP). The GRP provides complete interconnectivity
between all of these elements. The ispLSI 1016E offers
5V non-volatile in-system programmability of the logic, as
well as the interconnect to provide truly reconfigurable
systems. A functional superset of the ispLSI 1016
architecture, the ispLSI 1016E device adds a new global
output enable pin.
The basic unit of logic on the ispLSI 1016E device is the
Generic Logic Block (GLB). The GLBs are labeled A0,
A1...B7 (see Figure 1). There are a total of 16 GLBs in the
ispLSI 1016E device. Each GLB has 18 inputs, a
programmable AND/OR/Exclusive OR array, and four
outputs which can be configured to be either combinatorial
or registered. Inputs to the GLB come from the GRP and
dedicated inputs. All of the GLB outputs are brought back
into the GRP so that they can be connected to the inputs
of any other GLB on the device.
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control to
Minimize Switching Noise
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
— Lead-Free Package Options
U
Copyright © 2006 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
SE
is
p
LS
I1
A
FO
R
N
Description
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
August 2006
1016e_09
1
Output Routing Pool
N
0139C1-isp
A1
D Q
B6
S
A0
B7
LATTICE [ LATTICE SEMICONDUCTOR ]
