欢迎访问ic37.com |
会员登录 免费注册
发布采购

ISPLSI1032E-70LTI 参数 Datasheet PDF下载

ISPLSI1032E-70LTI图片预览
型号: ISPLSI1032E-70LTI
PDF下载: 下载PDF文件 查看货源
内容描述: 高密度可编程逻辑 [High-Density Programmable Logic]
分类和应用: 可编程逻辑器件输入元件时钟
文件页数/大小: 16 页 / 213 K
品牌: LATTICE [ LATTICE SEMICONDUCTOR ]
 浏览型号ISPLSI1032E-70LTI的Datasheet PDF文件第2页浏览型号ISPLSI1032E-70LTI的Datasheet PDF文件第3页浏览型号ISPLSI1032E-70LTI的Datasheet PDF文件第4页浏览型号ISPLSI1032E-70LTI的Datasheet PDF文件第5页浏览型号ISPLSI1032E-70LTI的Datasheet PDF文件第7页浏览型号ISPLSI1032E-70LTI的Datasheet PDF文件第8页浏览型号ISPLSI1032E-70LTI的Datasheet PDF文件第9页浏览型号ISPLSI1032E-70LTI的Datasheet PDF文件第10页  
Specifications
ispLSI and pLSI 1032E
External Timing Parameters
Over Recommended Operating Conditions
TEST
PARAMETER
COND.
4
#
2
1
2
3
4
5
6
7
8
9
DESCRIPTION
1
-90
90.0
1
tsu2 + tco1
-80
80.0
61.0
111
8.5
12.0
15.0
-70
15.0
17.5
7.0
8.0
15.0
18.0
18.0
12.0
12.0
MIN. MAX. MIN. MAX. MIN. MAX.
10.0
12.5
UNITS
ns
ns
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
pd1
t
pd2
f
max (Int.)
f
max (Ext.)
f
max (Tog.)
t
su1
t
co1
t
h1
t
su2
t
co2
t
h2
t
r1
t
rw1
t
ptoeen
t
ptoedis
t
goeen
t
goedis
t
wh
t
wl
t
su3
t
h3
1.
2.
3.
4.
A
A
A
A
A
B
C
B
C
Data Propagation Delay, 4PT Bypass, ORP Bypass
Data Propagation Delay, Worst Case Path
Clock Frequency with Internal Feedback
3
Clock Frequency with External Feedback
(
Clock Frequency, Max. Toggle
70.0
56.0
100
9.0
0.0
11.0
0.0
10.0
5.0
5.0
4.0
0.0
(
twh 1+ tw1
)
125
7.5
0.0
8.5
0.0
6.5
GLB Reg. Setup Time before Clock,4 PT Bypass
GLB Reg. Clock to Output Delay, ORP Bypass
GLB Reg. Hold Time after Clock, 4 PT Bypass
GLB Reg. Setup Time before Clock
10 GLB Reg. Clock to Output Delay
11 GLB Reg. Hold Time after Clock
12 Ext. Reset Pin to Output Delay
13 Ext. Reset Pulse Duration
14 Input to Output Enable
15 Input to Output Disable
16 Global OE Output Enable
17 Global OE Output Disable
18 External Synchronous Clock Pulse Duration, High
19 External Synchronous Clock Pulse Duration, Low
20
21
USE
4.0
4.0
I/O Reg. Setup Time before Ext. Sync Clock (Y2, Y3) 3.5
I/O Reg. Hold Time after Ext. Sync. Clock (Y2, Y3)
0.0
103
NEW 2E-10
DES 0 FOR
IGN
S
6.0
0.0
4.5
4.5
3.5
0.0
10.0
0.0
8.0
7.0
13.5
15.0
15.0
9.0
9.0
)
69.0
6.5
7.5
14.0
16.5
16.5
10.0
10.0
Unless noted otherwise, all parameters use the GRP, 20 PTXOR path, ORP and Y0 clock.
Refer to Timing Model in this data sheet for further details.
Standard 16-bit counter using GRP feedback.
Reference Switching Test Conditions section.
Table 2-0030B/1032E
6