Lead-
Free
Package
Options
Available!
ispLSI 1032E
®
In-System Programmable High Density PLD
Functional Block Diagram
Output Routing Pool
D7 D6 D5 D4 D3 D2 D1 D0
A0
D Q
Features
• HIGH DENSITY PROGRAMMABLE LOGIC
— 6000 PLD Gates
— 64 I/O Pins, Eight Dedicated Inputs
— 192 Registers
— High Speed Global Interconnect
C7
Output Routing Pool
A2
A3
A4
A5
A6
A7
D Q
— Small Logic Block Size for Random Logic
• HIGH PERFORMANCE
TECHNOLOGY
—
f
max
= 125 MHz Maximum Operating Frequency
—
t
pd
= 7.5 ns Propagation Delay
— TTL Compatible Inputs and Outputs
— Electrically Erasable and Reprogrammable
— Non-Volatile
— 100% Tested at Time of Manufacture
— Unused Product Term Shutdown Saves Power
• IN-SYSTEM PROGRAMMABLE
— In-System Programmable (ISP™) 5V Only
— Increased Manufacturing Yields, Reduced Time-to-
Market and Improved Product Quality
E
2
CMOS
®
Global Routing Pool (GRP)
B0 B1 B2 B3 B4 B5 B6 B7
N
EW
Output Routing Pool
0139A(A1)-isp
Description
— Reprogram Soldered Devices for Faster Prototyping
— Four Dedicated Clock Input Pins
03
— Enhanced Pin Locking Capability
2E
A
• OFFERS THE EASE OF USE AND FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY
OF FIELD PROGRAMMABLE GATE ARRAYS
— Complete Programmable Device Can Combine Glue
Logic and Structured Designs
The ispLSI 1032E is a High Density Programmable Logic
Device containing 192 Registers, 64 Universal I/O pins,
eight Dedicated Input pins, four Dedicated Clock Input
pins and a Global Routing Pool (GRP). The GRP
provides complete interconnectivity between all of these
elements. The ispLSI 1032E device offers 5V non-vola-
tile in-system programmability of the logic, as well as the
interconnects to provide truly reconfigurable systems. A
functional superset of the ispLSI 1032 architecture, the
ispLSI 1032E device adds two new global output enable
pins.
The basic unit of logic on the ispLSI 1032E device is the
Generic Logic Block (GLB). The GLBs are labeled A0,
A1…D7 (see Figure 1). There are a total of 32 GLBs in the
ispLSI 1032E device. Each GLB has 18 inputs, a pro-
grammable AND/OR/Exclusive OR array, and four outputs
which can be configured to be either combinatorial or
registered. Inputs to the GLB come from the GRP and
dedicated inputs. All of the GLB outputs are brought back
into the GRP so that they can be connected to the inputs
of any GLB on the device.
— Programmable Output Slew Rate Control to
Minimize Switching Noise
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
— Lead-Free Package Options
U
Copyright © 2006 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
SE
is
p
LS
I1
— Synchronous and Asynchronous Clocks
FO
R
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
1032e_09
1
D
ES
IG
D Q
Logic
Array
C5
GLB
C4
C3
C2
C1
C0
D Q
CLK
N
August 2006
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
Output Routing Pool
A1
C6
S
LATTICE [ LATTICE SEMICONDUCTOR ]
