Specifications ispLSI 1048E
Pin Description
NAME
PQFP / TQFP PIN NUMBERS
DESCRIPTION
I/O 0 - I/O 5
22,
28,
35,
41,
53,
59,
67,
73,
86,
92,
99,
23,
29,
36,
42,
54,
60,
68,
74,
87,
93,
100,
106,
119,
125,
4,
24,
30,
37,
43,
55,
61,
69,
75,
88,
94,
101,
107,
120,
126,
5,
25,
31,
38,
44,
56,
62,
70,
76,
89,
95,
102,
108,
121,
127,
6,
Input/Output Pins - These are the general purpose I/O pins used by the
logic array.
21,
27,
34,
40,
52,
58,
66,
72,
85,
91,
98,
26,
32,
39,
45,
57,
63,
71,
77,
90,
96,
103,
109,
122,
128,
7,
I/O 6 - I/O 11
I/O 12 - I/O 17
I/O 18 - I/O 23
I/O 24 - I/O 29
I/O 30 - I/O 35
I/O 36 - I/O 41
I/O 42 - I/O 47
I/O 48 - I/O 53
I/O 54 - I/O 59
I/O 60 - I/O 65
I/O 66 - I/O 71
I/O 72 - I/O 77
I/O 78 - I/O 83
I/O 84 - I/O 89
I/O 90 - I/O 95
104, 105,
117, 118,
123, 124,
2,
8,
3,
9,
10,
11,
12,
13
GOE0, GOE1
Global Output Enable input pins.
Dedicated input pins to the device.
64,
114
47,
84,
51
110,
IN 2, IN 4
IN 6 - IN 11
111, 115,
116, 14
ispEN
18
Input - Dedicated in-system programming enable input pin. This pin is
brought low to enable the programming mode. When low, the MODE,
SDI, SDO and SCLK controls become active.
Input - This pin performs two functions. When ispEN is logic low, it
functions as an input pin to load programming data into the device.
SDI/IN 0 also is used as one of the two control pins for the ISP state
machine. When ispEN is high, it functions as a dedicated input pin.
SDI/IN 01
20
MODE/IN 11
SDO/IN 31
SCLK/IN 51
46
50
78
Input - This pin performs two functions. When ispEN is logic low, it
functions as pin to control the operation of the isp state machine. When
ispEN is high, it functions as a dedicated input pin.
Output/Input - This pin performs two functions. When ispEN is logic low,
it functions as an output pin to read serial shift register data. When
ispEN is high, it functions as a dedicated input pin.
Input - This pin performs two functions. When ispEN is logic low, it
functions as a clock pin for the Serial Shift Register. When ispEN is
high, it functions as a dedicated input pin.
RESET
Y0
19
15
83
Active Low (0) Reset pin which resets all of the GLB and I/O registers in
the device.
Dedicated Clock input. This clock input is connected to one of the clock
inputs of all of the GLBs on the device.
Y1
Dedicated Clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any GLB on the
device.
Y2
Y3
80
79
Dedicated Clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any GLB and/or
any I/O cell on the device.
Dedicated Clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any I/O cell on the
device.
1,
17,
33,
82,
49,
65,
81,
GND
VCC
Ground (GND)
VCC
97,
112
16,
48,
113
Table 2 - 0002C-48E
1. Pins have dual function capability.
13
LATTICE [ LATTICE SEMICONDUCTOR ]
