Specifications
ispLSI 1048E
Internal Timing Parameters
1
PARAMETER
Inputs
#
2
-70
DESCRIPTION
-50
UNITS
MIN. MAX. MIN. MAX.
–
–
4.1
–
–
-0.6
0.6
3.6
–
–
–
–
6.5
–
–
-0.7
0.7
4.7
–
–
24 I/O Register Setup Time before Clock
25 I/O Register Hold Time after Clock
26 I/O Register Clock to Out Delay
27 I/O Register Reset to Out Delay
28 Dedicated Input Delay
29 GRP Delay, 1 GLB Load
30 GRP Delay, 4 GLB Loads
31 GRP Delay, 8 GLB Loads
32 GRP Delay, 16 GLB Loads
33 GRP Delay, 48 GLB Loads
D
ES
IG
6.0
6.0
4.3
–
–
t
iobp
t
iolat
t
iosu
t
ioh
t
ioco
t
ior
t
din
GRP
22 I/O Register Bypass
23 I/O Latch Delay
N
7.0
7.0
6.1
5.1
5.4
5.8
6.6
9.8
10.7
9.2
10.5
10.5
11.7
2.2
–
–
3.0
7.3
7.9
10.0
8.3
2.5
0.0
R
t
grp1
t
grp4
t
grp8
t
grp16
t
grp48
GLB
EW
–
–
–
–
–
–
–
–
–
–
–
0.1
8.5
–
–
–
–
5.1
–
–
3.5
3.7
4.1
4.8
7.5
8.5
7.4
8.4
8.4
9.4
1.6
–
–
2.0
6.3
6.1
6.8
6.4
2.0
0.0
–
–
–
–
–
–
–
–
–
–
–
0.0
11.5
–
–
–
–
6.9
–
–
N
ORP
SE
t
orp
t
orpbp
is
t
4ptbpc
t
4ptbpr
t
1ptxor
t
20ptxor
t
xoradj
t
gbp
t
gsu
t
gh
t
gco
t
gro
t
ptre
t
ptoe
t
ptck
34 4 Product Term Bypass Path Delay (Combinatorial)
35 4 Product Term Bypass Path Delay (Registered)
36 1 Product Term/XOR Path Delay
38 XOR Adjacent Path Delay
3
FO
EA
37 20 Product Term/XOR Path Delay
39 GLB Register Bypass Delay
48
41 GLB Register Hold Time after Clock
10
40 GLB Register Setup Time before Clock
42 GLB Register Clock to Output Delay
43 GLB Register Reset to Output Delay
44 GLB Product Term Reset to Register Delay
45 GLB Product Term Output Enable to I/O Cell Delay
46 GLB Product Term Clock Delay
47 ORP Delay
48 ORP Bypass Delay
SI
pL
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR adjacent path can only be used by hard macros.
U
Table 2-0036B/1048E
8
S
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
LATTICE [ LATTICE SEMICONDUCTOR ]
