Specifications
ispLSI 2032/A
External Timing Parameters
Over Recommended Operating Conditions
PARAMETER
TEST
#
2
COND.
A
A
A
–
–
–
A
–
–
–
–
A
–
B
C
B
C
–
–
4
DESCRIPTION
1
-180
–
–
180
5.0
7.5
–
–
–
–
–
–
–
–
–
–
-150
5.5
8.0
–
–
–
–
–
–
-135
7.5
10.0
–
–
–
–
4.5
–
–
5.5
–
10.0
–
12.0
12.0
6.0
6.0
–
–
MIN. MAX. MIN. MAX. MIN. MAX.
UNITS
ns
ns
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2E
t
pd1
t
pd2
f
max
f
max (Ext.)
f
max (Tog.)
t
su1
t
co1
t
h1
t
su2
t
co2
t
h2
t
r1
t
rw1
t
ptoeen
t
ptoedis
t
goeen
t
goedis
t
wh
t
wl
1.
2.
3.
4.
1 Data Prop. Delay, 4PT Bypass, ORP Bypass
2 Data Prop. Delay
3 Clk Frequency with Internal Feedback
3
4 Clk Frequency with Ext. Feedback
5 Clk Frequency, Max. Toggle
6 GLB Reg Setup Time before Clk, 4 PT Bypass
7 GLB Reg. Clk to Output Delay, ORP Bypass
8 GLB Reg. Hold Time after Clk, 4 PT Bypass
9 GLB Reg. Setup Time before Clk
10 GLB Reg. Clk to Output Delay
11 GLB Reg. Hold Time after Clk
12 Ext. Reset Pin to Output Delay
13 Ext. Reset Pulse Duration
14 Input to Output Enable
15 Input to Output Disable
16 Global OE Output Enable
17 Global OE Output Disable
154
111
167
3.0
–
137
100
167
4.0
–
0.0
5.5
–
0.0
–
5.0
–
–
–
–
3.0
3.0
(
1
tsu2 + tco1
)
125
200
3.0
–
0.0
4.0
–
0.0
–
–
–
–
–
2.5
2.5
4.0
4.0
4.5
7.0
EW
N
10.0
10.0
5.0
5.0
–
–
R
FO
18 Ext. Synchronous Clk Pulse Duration, High
19 Ext. Synchronous Clk Pulse Duration, Low
U
SE
is
p
LS
I2
03
Unless noted otherwise, all parameters use the GRP, 20 PTXOR path, ORP and Y0 clock.
Refer to Timing Model in this data sheet for further details.
Standard 16-bit counter using GRP feedback.
Reference Switching Test Conditions section.
5
D
ES
IG
4.5
–
–
–
8.0
–
11.0
11.0
5.0
5.0
–
–
0.0
–
4.5
5.0
0.0
–
4.5
–
–
–
–
3.0
3.0
N
Table 2-0030B-180/2032
S
LATTICE [ LATTICE SEMICONDUCTOR ]
