Specifications
ispLSI 2032/A
ispLSI 2032/A Timing Model
I/O Cell
GRP
Feedback
GLB
ORP
I/O Cell
Ded. In
#25, 26, 27
Reset
#45
D
RST
Q
#29, 30,
31, 32
EW
Control RE
PTs
OE
#33, 34, CK
35
Y0,1,2
GOE 0
#43, 44
#42
N
t
su
t
co
Note: Calculations are based upon timing specifications for the ispLSI 2032/A-180L
Table 2- 0042-16/2032
U
SE
is
p
LS
=
=
=
7.7 ns =
Clock (max) + Reg co + Output
(
t
io +
t
grp +
t
ptck(max)) + (
t
gco) + (
t
orp +
t
ob)
(#20+ #22+ #35) + (#31) + (#36 + #38)
(0.6 + 0.7 + 3.8) + (0.7) + (0.7 + 1.2)
I2
03
t
h
=
=
=
1.5 ns =
Clock (max) + Reg h - Logic
(
t
io +
t
grp +
t
ptck(max)) + (
t
gh) - (
t
io +
t
grp +
t
20ptxor)
(#20+ #22+ #35) + (#30) - (#20+ #22+ #26)
(0.6 + 0.7 + 3.8) + (1.8) - (0.6 + 0.7 + 4.1)
2E
=
=
=
2.1 ns =
Logic + Reg su - Clock (min)
(
t
io +
t
grp +
t
20ptxor) + (
t
gsu) - (
t
io +
t
grp +
t
ptck(min))
(#20+ #22+ #26) + (#29) - (#20+ #22+ #35)
(0.6 + 0.7 + 4.1) + (0.5) - (0.6 + 0.7 + 2.5)
FO
Derivations of
t
su,
t
h and
t
co from the Product Term Clock
1
9
R
D
ES
IG
#36
#40, 41
0491/2000
20 PT
XOR Delays
GLB Reg
Delay
ORP
Delay
N
I/O Pin
(Input)
I/O Delay
#20
GRP
#22
Reg 4 PT Bypass
#24
GLB Reg Bypass
#28
ORP Bypass
#37
#38,
39
S
#21
Comb 4 PT Bypass #23
I/O Pin
(Output)
LATTICE [ LATTICE SEMICONDUCTOR ]
