Specifications ispLSI 2064V
Functional Block Diagram
Figure 1. ispLSI 2064V Functional Block Diagram (64-I/O and 32-I/O Versions)
Generic Logic
Blocks (GLBs)
Generic Logic
Blocks (GLBs)
Input Bus
Input Bus
Output Routing Pool (ORP)
B6 B5
Output Routing Pool (ORP)
Megablock
Megablock
B7
B4
B7
B6
B5
B4
I/O 47
I/O 46
I/O 45
I/O 44
I/O 23
I/O 22
I/O 21
I/O 20
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
A0
A1
A2
B3
B2
B1
B0
A0
A1
A2
B3
B2
B1
B0
I/O 4
I/O 5
I/O 6
I/O 7
I/O 43
I/O 42
I/O 41
I/O 40
Global Routing Pool
(GRP)
Global Routing Pool
(GRP)
I/O 8
I/O 9
I/O 39
I/O 38
I/O 37
I/O 36
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
I/O 35
I/O 34
I/O 33
I/O 32
I/O 4
I/O 5
I/O 6
I/O 7
I/O 19
I/O 18
I/O 17
I/O 16
A3
A3
GOE0/IN 3
TMS/IN 2
TCK/IN 3
TDO/IN 2
TDI/IN 0
TMS/IN 1
TDI/IN 0
A4
A5
A6
A7
A4
A5
A6
A7
TDO/IN 1
Output Routing Pool (ORP)
Input Bus
Output Routing Pool (ORP)
Input Bus
RESET
ispEN
ispEN
0139B/2064V
0139B/2064V.32IO
The 64-I/O 2064V contains 64 I/O cells, while the 32-I/O Y2) or an asynchronous clock can be selected on a GLB
version contains 32 I/O cells. Each I/O cell is directly basis. The asynchronous or Product Term clock can be
connected to an I/O pin and can be individually pro- generated in any GLB for its own clock.
grammed to be a combinatorial input, output or
Programmable Open-Drain Outputs
bi-directional I/O pin with 3-state control. The signal
levelsareTTLcompatiblevoltagesandtheoutputdrivers
can source 4 mA or sink 8 mA. Each output can be
programmed independently for fast or slow output slew
rate to minimize overall output switching noise. Device
pins can be safely driven to 5-Volt signal levels to support
mixed-voltage systems.
In addition to the standard output configuration, the
outputs of the ispLSI 2064V are individually program-
mable, either as a standard totem-pole output or an
open-drain output. The totem-pole output drives the
specified Voh and Vol levels, whereas the open-drain
output drives only the specified Vol. The Voh level on the
open-drain output depends on the external loading and
pull-up. This output configuration is controlled by a pro-
grammable fuse. When this fuse is erased (JEDEC “1”),
the output is configured as a totem-pole output. When
this fuse is programmed (JEDEC “0”), the output is
configured as an open-drain. The default configuration
when the device is in bulk erased state is totem-pole
configuration. The open-drain/totem-pole option is se-
lectable through the ispDesignEXPERT software tools.
Eight GLBs, 32 or 16 I/O cells, two dedicated inputs and
two or one ORPs are connected together to make a
Megablock (see Figure 1). The outputs of the eight GLBs
are connected to a set of 32 or 16 universal I/O cells by
two or one ORPs. Each ispLSI 2064V device contains
two Megablocks.
The GRP has as its inputs, the outputs from all of the
GLBsandallof theinputsfromthebi-directionalI/O cells.
All of these signals are made available to the inputs of the
GLBs. Delays through the GRP have been equalized to
minimize timing skew.
Clocks in the ispLSI 2064V device are selected using the
dedicatedclockpins. Threededicatedclockpins(Y0, Y1,
2
LATTICE [ LATTICE SEMICONDUCTOR ]
