欢迎访问ic37.com |
会员登录 免费注册
发布采购

LC4064V-10TN48I 参数 Datasheet PDF下载

LC4064V-10TN48I图片预览
型号: LC4064V-10TN48I
PDF下载: 下载PDF文件 查看货源
内容描述: 3.3V / 2.5V / 1.8V在系统可编程超快高密度可编程逻辑器件 [3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs]
分类和应用: 可编程逻辑器件
文件页数/大小: 99 页 / 451 K
品牌: LATTICE [ LATTICE SEMICONDUCTOR ]
 浏览型号LC4064V-10TN48I的Datasheet PDF文件第2页浏览型号LC4064V-10TN48I的Datasheet PDF文件第3页浏览型号LC4064V-10TN48I的Datasheet PDF文件第4页浏览型号LC4064V-10TN48I的Datasheet PDF文件第5页浏览型号LC4064V-10TN48I的Datasheet PDF文件第6页浏览型号LC4064V-10TN48I的Datasheet PDF文件第7页浏览型号LC4064V-10TN48I的Datasheet PDF文件第8页浏览型号LC4064V-10TN48I的Datasheet PDF文件第9页  
ispMACH 4000V/B/C/Z Family
®
November 2007
Coolest Power
C
TM
3.3V/2.5V/1.8V In-System Programmable
SuperFAST
TM
High Density PLDs
Data Sheet DS1020
Features
High Performance
Broad Device Offering
• Multiple temperature range support
– Commercial: 0 to 90°C junction (T
j
)
– Industrial: -40 to 105°C junction (T
j
)
– Extended: -40 to 130°C junction (T
j
)
• For AEC-Q100 compliant devices, refer to
LA-ispMACH 4000V/Z Automotive Data Sheet
• f
MAX
= 400MHz maximum operating frequency
• t
PD
= 2.5ns propagation delay
• Up to four global clock pins with programmable
clock polarity control
• Up to 80 PTs per output
Ease of Design
• Enhanced macrocells with individual clock,
reset, preset and clock enable controls
• Up to four global OE controls
• Individual local OE control per I/O pin
• Excellent First-Time-Fit
TM
and refit
• Fast path, SpeedLocking
TM
Path, and wide-PT
path
• Wide input gating (36 input logic blocks) for fast
counters, state machines and address decoders
Easy System Integration
• Superior solution for power sensitive consumer
applications
• Operation with 3.3V, 2.5V or 1.8V LVCMOS I/O
• Operation with 3.3V (4000V), 2.5V (4000B) or
1.8V (4000C/Z) supplies
• 5V tolerant I/O for LVCMOS 3.3, LVTTL, and PCI
interfaces
• Hot-socketing
• Open-drain capability
• Input pull-up, pull-down or bus-keeper
• Programmable output slew rate
• 3.3V PCI compatible
• IEEE 1149.1 boundary scan testable
• 3.3V/2.5V/1.8V In-System Programmable
(ISP™) using IEEE 1532 compliant interface
• I/O pins with fast setup path
• Lead-free package options
Zero Power (ispMACH 4000Z) and Low
Power (ispMACH 4000V/B/C)
Typical static current 10µA (4032Z)
Typical static current 1.3mA (4000C)
1.8V core low dynamic power
ispMACH 4000Z operational down to 1.6V V
CC
Table 1. ispMACH 4000V/B/C Family Selection Guide
ispMACH
4032V/B/C
Macrocells
I/O + Dedicated Inputs
t
PD
(ns)
t
S
(ns)
t
CO
(ns)
f
MAX
(MHz)
Supply Voltages (V)
Pins/Package
32
30+2/32+4
2.5
1.8
2.2
400
3.3/2.5/1.8V
44 TQFP
48 TQFP
ispMACH
4064V/B/C
64
30+2/32+4/
64+10
2.5
1.8
2.2
400
3.3/2.5/1.8V
44 TQFP
48 TQFP
100 TQFP
ispMACH
4128V/B/C
128
64+10/92+4/
96+4
2.7
1.8
2.7
333
3.3/2.5/1.8V
ispMACH
4256V/B/C
256
64+10/96+14/
128+4/160+4
3.0
2.0
2.7
322
3.3/2.5/1.8V
ispMACH
4384V/B/C
384
128+4/192+4
3.5
2.0
2.7
322
3.3/2.5/1.8V
ispMACH
4512V/B/C
512
128+4/208+4
3.5
2.0
2.7
322
3.3/2.5/1.8V
100 TQFP
128 TQFP
144 TQFP
1
100 TQFP
144 TQFP
1
176 TQFP
256 ftBGA
2
/
fpBGA
2, 3
176 TQFP
256 ftBGA/
fpBGA
3
176 TQFP
256 ftBGA/
fpBGA
3
1. 3.3V (4000V) only.
2. 128-I/O and 160-I/O configurations.
3. Use 256 ftBGA package for all new designs. Refer to PCN#14A-07 for 256 fpBGA package discontinuance.
© 2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
1
DS1020_23.0