Table 7. Logic Allocation for MACH211(SP) and MACH231(SP)
Macrocell
Output
M
0
M
1
M
2
M
3
M
4
M
5
M
6
M
7
Buried
Available Clusters
C
0
, C
1
, C
2
C
0
, C
1
, C
2
, C
3
C
1
, C
2
, C
3
, C
4
C
2
, C
3
, C
4
, C
5
C
3
, C
4
, C
5
, C
6
C
4
, C
5
, C
6
, C
7
C
5
, C
6
, C
7
, C
8
C
6
, C
7
, C
8
, C
9
M
8
M
9
M
10
M
11
M
12
M
13
M
14
M
15
Macrocell
Output
Buried
Available Clusters
C
7
, C
8
, C
9
, C
10
C
8
, C
9
, C
10
, C
11
C
9
, C
10
, C
11
, C
12
C
10
, C
11
, C
12
, C
13
C
11
, C
12
, C
13
, C
14
C
12
, C
13
, C
14
, C
15
C
13
, C
14
, C
15
C
14
, C
15
Table 8. Logic Allocation for MACH221(SP)
Macrocell
Output
M
0
M
1
M
2
M
3
M
4
M
5
Buried
Available Clusters
C
0
, C
1
, C
2
C
0
, C
1
, C
2
, C
3
C
1
, C
2
, C
3
, C
4
C
2
, C
3
, C
4
, C
5
C
3
, C
4
, C
5
, C
6
C
4
, C
5
, C
6
, C
7
M
6
M
7
M
8
M
9
M
10
M
11
Macrocell
Output
Buried
Available Clusters
C
5
, C
6
, C
7
, C
8
C
6
, C
7
, C
8
, C
9
C
7
, C
8
, C
9
, C
10
C
8
, C
9
, C
10
, C
11
C
9
, C
10
, C
11
C
10
, C
11
Macrocell
There are two fundamental types of macrocell: the output macrocell and the buried macrocell. The
buried macrocell is only found in MACH 2 devices. The use of buried macrocells effectively
doubles the number of macrocells available without increasing the pin count.
Both macrocell types can generate registered or combinatorial outputs. For the MACH 2 series,
a transparent-low latch configuration is provided. If the register is used, it can be configured as
a T-type or a D-type flip-flop. Register and latch functionality is defined in Table 9.
Programmable polarity (for output macrocells) and the T-type flip-flop both give the software a
way to minimize the number of product terms needed. These choices can be made automatically
by the software when it fits the design into the device.
Table 9. Register/Latch Operation
Configuration
D-Register
D/T
X
0
1
X
T-Register
0
1
X
Latch
0
1
CLK/LE
0,1,↓
↑
↑
0,1,↓
↑
↑
1
0
0
Q+
Q
0
1
Q
Q
Q
Q
0
1
MACH 1 & 2 Families
7
LATTICE [ LATTICE SEMICONDUCTOR ]
